fsp_baytrail: Add the FSP version of Intel's Bay Trail-I chip

While similar to the Bay Trail-M/D code based on the MRC, there are
many differences as well:
- Obviously, uses the FSP instead of the MRC binaries.
- FSP does additional hardware setup, so coreboot doesn't need to.
- Different microcode & microcode loading method
- Uses the cache_as_ram.inc from the FSP Driver
- Various other changes in support of the FSP
Additional changes that don't have to to with the FSP vs MRC:
- Updated IRQ Routing
- Different FADT implementation.
This was validated with FSP:
BAYTRAIL_FSP_GOLD_002_10-JANUARY-2014.fd
SHA256: d29eefbb33454bd5314bfaa38fb055d592a757de7b348ed7096cd8c2d65908a5
MD5: 9360cd915f0d3e4116bbc782233d7b91

Change-Id: Iadadf8cd6cf444ba840e0f76d3aed7825cd7aee4
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5791
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 138 insertions, 0 deletions

diff --git a/src/soc/intel/fsp_baytrail/ramstage.c b/src/soc/intel/fsp_baytrail/ramstage.c
new file mode 100644
index 0000000000..e23170136e
--- /dev/null
+++ b/src/soc/intel/fsp_baytrail/ramstage.c
@@ -0,0 +1,138 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/cpu.h>
+#include <console/console.h>
+#include <cpu/intel/microcode.h>
+#include <cpu/x86/cr.h>
+#include <cpu/x86/msr.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <stdlib.h>
+
+#include <baytrail/gpio.h>
+#include <baytrail/lpc.h>
+#include <baytrail/msr.h>
+#include <baytrail/pattrs.h>
+#include <baytrail/pci_devs.h>
+#include <baytrail/ramstage.h>
+
+/* Global PATTRS */
+DEFINE_PATTRS;
+
+#define SHOW_PATTRS 1
+
+static void detect_num_cpus(struct pattrs *attrs)
+{
+	int ecx = 0;
+
+	while (1) {
+		struct cpuid_result leaf_b;
+
+		leaf_b = cpuid_ext(0xb, ecx);
+
+		/* Bay Trail doesn't have hyperthreading so just determine the
+		 * number of cores by from level type (ecx[15:8] == * 2). */
+		if ((leaf_b.ecx & 0xff00) == 0x0200) {
+			attrs->num_cpus = leaf_b.ebx & 0xffff;
+			break;
+		}
+		ecx++;
+	}
+}
+
+static inline void fill_in_msr(msr_t *msr, int idx)
+{
+	*msr = rdmsr(idx);
+	if (SHOW_PATTRS) {
+		printk(BIOS_DEBUG, "msr(%x) = %08x%08x\n",
+		       idx, msr->hi, msr->lo);
+	}
+}
+
+static const char *stepping_str[] = {
+	"A0", "A1", "B0", "B1", "B2", "B3"
+};
+
+static void fill_in_pattrs(void)
+{
+	device_t dev;
+	msr_t msr;
+	struct pattrs *attrs = (struct pattrs *)pattrs_get();
+
+	attrs->cpuid = cpuid_eax(1);
+	dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
+	attrs->revid = pci_read_config8(dev, REVID);
+	/* The revision to stepping IDs have two values per metal stepping. */
+	if (attrs->revid >= RID_B_STEPPING_START) {
+		attrs->stepping = (attrs->revid - RID_B_STEPPING_START) / 2;
+		attrs->stepping += STEP_B0;
+	} else {
+		attrs->stepping = (attrs->revid - RID_A_STEPPING_START) / 2;
+		attrs->stepping += STEP_A0;
+	}
+
+	attrs->address_bits = cpuid_eax(0x80000008) & 0xff;
+	detect_num_cpus(attrs);
+
+	if (SHOW_PATTRS) {
+		printk(BIOS_DEBUG,
+		       "CPUID: %08x\nCores: %d\nRevision ID: %02x\nStepping: %s\n",
+		       attrs->cpuid, attrs->num_cpus, attrs->revid,
+		       (attrs->stepping >= ARRAY_SIZE(stepping_str)) ? "??" :
+		       stepping_str[attrs->stepping]);
+	}
+
+	fill_in_msr(&attrs->platform_id, MSR_IA32_PLATFORM_ID);
+	fill_in_msr(&attrs->platform_info, MSR_PLATFORM_INFO);
+
+	/* Set IA core speed ratio and voltages */
+	msr = rdmsr(MSR_IACORE_RATIOS);
+	attrs->iacore_ratios[IACORE_MIN] = msr.lo & 0x7f;
+	attrs->iacore_ratios[IACORE_LFM] = (msr.lo >> 8) & 0x7f;
+	attrs->iacore_ratios[IACORE_MAX] = (msr.lo >> 16) & 0x7f;
+	msr = rdmsr(MSR_IACORE_TURBO_RATIOS);
+	attrs->iacore_ratios[IACORE_TURBO] = (msr.lo & 0xff); /* 1 core max */
+
+	msr = rdmsr(MSR_IACORE_VIDS);
+	attrs->iacore_vids[IACORE_MIN] = msr.lo & 0x7f;
+	attrs->iacore_vids[IACORE_LFM] = (msr.lo >> 8) & 0x7f;
+	attrs->iacore_vids[IACORE_MAX] = (msr.lo >> 16) & 0x7f;
+	msr = rdmsr(MSR_IACORE_TURBO_VIDS);
+	attrs->iacore_vids[IACORE_TURBO] = (msr.lo & 0xff); /* 1 core max */
+
+	/* Set bus clock speed */
+	attrs->bclk_khz = bus_freq_khz();
+}
+
+
+void baytrail_init_pre_device(void)
+{
+	struct soc_gpio_config *config;
+
+	fill_in_pattrs();
+
+	/* Allow for SSE instructions to be executed. */
+	write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT);
+
+	/* Get GPIO initial states from mainboard */
+	config = mainboard_get_gpios();
+	setup_soc_gpios(config);
+}