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author | Aaron Durbin <adurbin@chromium.org> | 2016-07-13 23:22:01 -0500 |
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committer | Aaron Durbin <adurbin@chromium.org> | 2016-07-15 08:33:03 +0200 |
commit | 15e439a72e26b72394b14e3777541819468bc10c (patch) | |
tree | 0b70bf36407656572248332e647b33636d0ca66f /src/soc/intel/fsp_baytrail/romstage | |
parent | 9e6d143a82a852ddfa64f20ceb8695939c1dace1 (diff) | |
download | coreboot-15e439a72e26b72394b14e3777541819468bc10c.tar.xz |
soc/intel/fsp_baytrail: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.
BUG=chrome-os-partner:54977
Change-Id: I1ff1517ded2d43e3790d980599e756d0d064f75c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15674
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/fsp_baytrail/romstage')
-rw-r--r-- | src/soc/intel/fsp_baytrail/romstage/romstage.c | 27 |
1 files changed, 13 insertions, 14 deletions
diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index 4de98d313a..881ad0b9b5 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -44,7 +44,7 @@ uint32_t chipset_prev_sleep_state(uint32_t clear) { /* Default to S0. */ - uint32_t prev_sleep_state = 0; + uint32_t prev_sleep_state = ACPI_S0; uint32_t pm1_sts; uint32_t pm1_cnt; uint32_t gen_pmcon1; @@ -58,18 +58,17 @@ uint32_t chipset_prev_sleep_state(uint32_t clear) pm1_sts, pm1_cnt, gen_pmcon1); if (pm1_sts & WAK_STS) { - switch ((pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) { - #if CONFIG_HAVE_ACPI_RESUME - case SLP_TYP_S3: - prev_sleep_state = 3; + switch (acpi_sleep_from_pm1(pm1_cnt)) { + case ACPI_S3: + if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) + prev_sleep_state = ACPI_S3; break; - #endif - case SLP_TYP_S4: - prev_sleep_state = 4; + case ACPI_S4: + prev_sleep_state = ACPI_S4; break; - case SLP_TYP_S5: - prev_sleep_state = 5; + case ACPI_S5: + prev_sleep_state = ACPI_S5; break; } /* If set Clear SLP_TYP. */ @@ -79,7 +78,7 @@ uint32_t chipset_prev_sleep_state(uint32_t clear) } if (gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR)) { - prev_sleep_state = 5; + prev_sleep_state = ACPI_S5; } return prev_sleep_state; @@ -246,12 +245,12 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) post_code(0x4c); /* if S3 resume skip ram check */ - if (prev_sleep_state != 3) { + if (prev_sleep_state != ACPI_S3) { quick_ram_check(); post_code(0x4d); } - cbmem_was_initted = !cbmem_recovery(prev_sleep_state == 3); + cbmem_was_initted = !cbmem_recovery(prev_sleep_state == ACPI_S3); /* Save the HOB pointer in CBMEM to be used in ramstage*/ cbmem_hob_ptr = cbmem_add (CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr)); @@ -260,7 +259,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) handoff = romstage_handoff_find_or_add(); if (handoff != NULL) - handoff->s3_resume = (prev_sleep_state == 3); + handoff->s3_resume = (prev_sleep_state == ACPI_S3); else printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); |