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author | Ben Gardner <gardner.ben@gmail.com> | 2015-12-08 21:20:25 -0600 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2015-12-16 01:10:06 +0100 |
commit | fa6014a6ec8253de8c86b0180221856a1398e70b (patch) | |
tree | 55d71de574980b69930abed6bf3733050e6b69ac /src/soc/intel/fsp_baytrail/tsc_freq.c | |
parent | 1e1c7ac3b4cb6d85eb602e04b0e4da8c042846c0 (diff) | |
download | coreboot-fa6014a6ec8253de8c86b0180221856a1398e70b.tar.xz |
intel/fsp_baytrail: rename include folder baytrail to include/soc
This is to match the layout of the non-fsp baytrail to make comparisons
easier and possibly remove duplicate files.
Change-Id: I9a94842d724ab3826de711d398227e7bdc1045ff
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/12686
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/soc/intel/fsp_baytrail/tsc_freq.c')
-rw-r--r-- | src/soc/intel/fsp_baytrail/tsc_freq.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/fsp_baytrail/tsc_freq.c b/src/soc/intel/fsp_baytrail/tsc_freq.c index f002187b10..66fde22d99 100644 --- a/src/soc/intel/fsp_baytrail/tsc_freq.c +++ b/src/soc/intel/fsp_baytrail/tsc_freq.c @@ -16,7 +16,7 @@ #include <stdint.h> #include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> -#include <baytrail/msr.h> +#include <soc/msr.h> unsigned bus_freq_khz(void) { @@ -49,9 +49,9 @@ unsigned long tsc_freq_mhz(void) #if !defined(__SMM__) #if !defined(__PRE_RAM__) -#include <baytrail/ramstage.h> +#include <soc/ramstage.h> #else -#include <baytrail/romstage.h> +#include <soc/romstage.h> #endif void set_max_freq(void) |