summaryrefslogtreecommitdiff
path: root/src/soc/intel/fsp_baytrail
diff options
context:
space:
mode:
authorMartin Roth <martin.roth@se-eng.com>2014-11-16 20:07:16 -0700
committerMartin Roth <gaumless@gmail.com>2014-12-05 16:21:06 +0100
commit8d936ce8538d814c5981d3ac5677b53fc1b90272 (patch)
tree3229825f7cf843e18235dacc42f7fe1b3ed767b0 /src/soc/intel/fsp_baytrail
parente8d1901134f01434b09f5edb790ac8465305db1c (diff)
downloadcoreboot-8d936ce8538d814c5981d3ac5677b53fc1b90272.tar.xz
fsp_baytrail: update for UPD_SPD_CHECK macro
Update chipset_fsp_util.c to use the UPD_SPD_CHECK macro. This makes the code more standardized and easier to read. Change-Id: I9944e1a4df82e64a205598e98ed0f3b840af1019 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7489 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/fsp_baytrail')
-rw-r--r--src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c13
1 files changed, 2 insertions, 11 deletions
diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
index c69076cb6d..3aabdaa546 100644
--- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
+++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
@@ -83,17 +83,8 @@ static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *U
UpdData->AzaliaConfigPtr = (UINT32)&mAzaliaConfig;
/* Set SPD addresses */
- if (config->PcdMrcInitSPDAddr1 == SPD_ADDR_DISABLED)
- UpdData->PcdMrcInitSPDAddr1 = 0x00;
- else if (config->PcdMrcInitSPDAddr1 != SPD_ADDR_DEFAULT)
- UpdData->PcdMrcInitSPDAddr1 = config->PcdMrcInitSPDAddr1;
- printk(BIOS_DEBUG, "SPD Addr1:\t\t0x%02x\n", UpdData->PcdMrcInitSPDAddr1);
-
- if (config->PcdMrcInitSPDAddr2 == SPD_ADDR_DISABLED)
- UpdData->PcdMrcInitSPDAddr2 = 0x00;
- else if (config->PcdMrcInitSPDAddr2 != SPD_ADDR_DEFAULT)
- UpdData->PcdMrcInitSPDAddr2 = config->PcdMrcInitSPDAddr2;
- printk(BIOS_DEBUG, "SPD Addr2:\t\t0x%02x\n", UpdData->PcdMrcInitSPDAddr2);
+ UPD_SPD_CHECK(PcdMrcInitSPDAddr1);
+ UPD_SPD_CHECK(PcdMrcInitSPDAddr2);
UPD_DEFAULT_CHECK(PcdSataMode);
UPD_DEFAULT_CHECK(PcdLpssSioEnablePciMode);