coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)

This patch is a raw application of

 find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'

Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

11 files changed, 20 insertions, 20 deletions

diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c
index 9701a338eb..371581b77a 100644
--- a/src/soc/intel/fsp_baytrail/acpi.c
+++ b/src/soc/intel/fsp_baytrail/acpi.c
@@ -89,7 +89,7 @@ void acpi_init_gnvs(global_nvs_t *gnvs)
 	/* Top of Low Memory (start of resource allocation) */
 	gnvs->tolm = nc_read_top_of_low_memory();
 
-#if IS_ENABLED(CONFIG_CONSOLE_CBMEM)
+#if CONFIG(CONSOLE_CBMEM)
 	/* Update the mem console pointer. */
 	gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
 #endif
diff --git a/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl b/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl
index ae958c2f01..8e47f5c7a0 100644
--- a/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl
+++ b/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl
@@ -16,7 +16,7 @@
 
 Name(\_S0, Package(){0x0,0x0,0x0,0x0})
 // Name(\_S1, Package(){0x1,0x1,0x0,0x0})
-#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+#if CONFIG(HAVE_ACPI_RESUME)
 Name(\_S3, Package(){0x5,0x5,0x0,0x0})
 #endif
 Name(\_S4, Package(){0x6,0x6,0x0,0x0})
diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c
index 89ea4c2ada..15dc851b96 100644
--- a/src/soc/intel/fsp_baytrail/cpu.c
+++ b/src/soc/intel/fsp_baytrail/cpu.c
@@ -150,7 +150,7 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase,
 
 static void enable_smis(void)
 {
-	if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER))
+	if (CONFIG(HAVE_SMI_HANDLER))
 		southcluster_smm_enable_smi();
 }
 
diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
index 3786c0cc35..c9cbcfe960 100644
--- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
+++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
@@ -307,7 +307,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams,
 	ConfigureDefaultUpdData(fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr);
 	pFspInitParams->NvsBufferPtr = NULL;
 
-#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)
+#if CONFIG(ENABLE_MRC_CACHE)
 	/* Find the fastboot cache that was saved in the ROM */
 	pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache();
 #endif
diff --git a/src/soc/intel/fsp_baytrail/gpio.c b/src/soc/intel/fsp_baytrail/gpio.c
index 282083aa55..8d4e090a40 100644
--- a/src/soc/intel/fsp_baytrail/gpio.c
+++ b/src/soc/intel/fsp_baytrail/gpio.c
@@ -207,7 +207,7 @@ static void setup_gpio_route(const struct soc_gpio_map *sus,
 		}
 	}
 
-#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
+#if CONFIG(HAVE_SMI_HANDLER)
 	southcluster_smm_save_gpio_route(route_reg);
 #endif
 }
diff --git a/src/soc/intel/fsp_baytrail/include/soc/pmc.h b/src/soc/intel/fsp_baytrail/include/soc/pmc.h
index b28b195c87..75daba540e 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/pmc.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/pmc.h
@@ -283,7 +283,7 @@ void enable_gpe(uint32_t mask);
 void disable_gpe(uint32_t mask);
 void disable_all_gpe(void);
 
-#if IS_ENABLED(CONFIG_ELOG)
+#if CONFIG(ELOG)
 void southcluster_log_state(void);
 #else
 static inline void southcluster_log_state(void) {}
diff --git a/src/soc/intel/fsp_baytrail/include/soc/romstage.h b/src/soc/intel/fsp_baytrail/include/soc/romstage.h
index ce66df8a6a..9cbc95c240 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/romstage.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/romstage.h
@@ -39,7 +39,7 @@ void early_mainboard_romstage_entry(void);
 void late_mainboard_romstage_entry(void);
 void get_func_disables(uint32_t *mask, uint32_t *mask2);
 
-#if IS_ENABLED(CONFIG_ENABLE_BUILTIN_COM1)
+#if CONFIG(ENABLE_BUILTIN_COM1)
 void byt_config_com1_and_enable(void);
 #else
 static inline void byt_config_com1_and_enable(void) { }
diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c
index 62cc189b60..b4eb006aab 100644
--- a/src/soc/intel/fsp_baytrail/romstage/romstage.c
+++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c
@@ -63,7 +63,7 @@ uint32_t chipset_prev_sleep_state(uint32_t clear)
 	if (pm1_sts & WAK_STS) {
 		switch (acpi_sleep_from_pm1(pm1_cnt)) {
 		case ACPI_S3:
-			if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME))
+			if (CONFIG(HAVE_ACPI_RESUME))
 				prev_sleep_state = ACPI_S3;
 			break;
 		case ACPI_S4:
@@ -229,7 +229,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr)
 		__func__, (u32) status, (u32) hob_list_ptr);
 
 	/* FSP reconfigures USB, so reinit it to have debug */
-	if (IS_ENABLED(CONFIG_USBDEBUG_IN_PRE_RAM))
+	if (CONFIG(USBDEBUG_IN_PRE_RAM))
 		usbdebug_hw_init(true);
 
 	printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status);
diff --git a/src/soc/intel/fsp_baytrail/smihandler.c b/src/soc/intel/fsp_baytrail/smihandler.c
index ee0929d83d..f2abd9975a 100644
--- a/src/soc/intel/fsp_baytrail/smihandler.c
+++ b/src/soc/intel/fsp_baytrail/smihandler.c
@@ -111,7 +111,7 @@ static void southbridge_smi_sleep(void)
 	/* Do any mainboard sleep handling */
 	mainboard_smi_sleep(slp_typ);
 
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
 	/* Log S3, S4, and S5 entry */
 	if (slp_typ >= ACPI_S3)
 		elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
@@ -207,7 +207,7 @@ static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd)
 	return NULL;
 }
 
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
 static void southbridge_smi_gsmi(void)
 {
 	u32 *ret, *param;
@@ -274,7 +274,7 @@ static void southbridge_smi_apmc(void)
 			printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
 		}
 		break;
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
 	case APM_CNT_ELOG_GSMI:
 		southbridge_smi_gsmi();
 		break;
@@ -293,7 +293,7 @@ static void southbridge_smi_pm1(void)
 	 */
 	if (pm1_sts & PWRBTN_STS) {
 		// power button pressed
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
 		elog_add_event(ELOG_TYPE_POWER_BUTTON);
 #endif
 		disable_pm1_control(-1UL);
diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c
index 8fce928a2d..e6947b4d6d 100644
--- a/src/soc/intel/fsp_baytrail/southcluster.c
+++ b/src/soc/intel/fsp_baytrail/southcluster.c
@@ -139,7 +139,7 @@ static void sc_enable_serial_irqs(struct device *dev)
 	write32(ibase + ILB_OIC, read32(ibase + ILB_OIC) | SIRQEN);
 	write8(ibase + ILB_SERIRQ_CNTL, SCNT_CONTINUOUS_MODE);
 
-#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)
+#if !CONFIG(SERIRQ_CONTINUOUS_MODE)
 	/*
 	 * SoC requires that the System BIOS first set the SERIRQ logic to
 	 * continuous mode operation for at least one frame before switching
diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c
index 4bc924c500..573c1c4390 100644
--- a/src/soc/intel/fsp_baytrail/spi.c
+++ b/src/soc/intel/fsp_baytrail/spi.c
@@ -138,7 +138,7 @@ enum {
 static uint8_t readb_(const void *addr)
 {
 	uint8_t v = read8(addr);
-	if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) {
+	if (CONFIG(DEBUG_SPI_FLASH)) {
 		printk(BIOS_DEBUG, "SPI: read %2.2x from %4.4x\n",
 				v, (((uint32_t) addr) & SPI_OFFSET_MASK));
 	}
@@ -148,7 +148,7 @@ static uint8_t readb_(const void *addr)
 static uint16_t readw_(const void *addr)
 {
 	uint16_t v = read16(addr);
-	if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) {
+	if (CONFIG(DEBUG_SPI_FLASH)) {
 		printk(BIOS_DEBUG, "SPI: read %4.4x from %4.4x\n",
 				v, (((uint32_t) addr) & SPI_OFFSET_MASK));
 	}
@@ -158,7 +158,7 @@ static uint16_t readw_(const void *addr)
 static uint32_t readl_(const void *addr)
 {
 	uint32_t v = read32(addr);
-	if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) {
+	if (CONFIG(DEBUG_SPI_FLASH)) {
 		printk(BIOS_DEBUG, "SPI: read %8.8x from %4.4x\n",
 				v, (((uint32_t) addr) & SPI_OFFSET_MASK));
 	}
@@ -168,7 +168,7 @@ static uint32_t readl_(const void *addr)
 static void writeb_(uint8_t b, void *addr)
 {
 	write8(addr, b);
-	if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) {
+	if (CONFIG(DEBUG_SPI_FLASH)) {
 		printk(BIOS_DEBUG, "SPI: wrote %2.2x to %4.4x\n",
 				b, (((uint32_t) addr) & SPI_OFFSET_MASK));
 	}
@@ -177,7 +177,7 @@ static void writeb_(uint8_t b, void *addr)
 static void writew_(uint16_t b, void *addr)
 {
 	write16(addr, b);
-	if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) {
+	if (CONFIG(DEBUG_SPI_FLASH)) {
 		printk(BIOS_DEBUG, "SPI: wrote %4.4x to %4.4x\n",
 				b, (((uint32_t) addr) & SPI_OFFSET_MASK));
 	}
@@ -186,7 +186,7 @@ static void writew_(uint16_t b, void *addr)
 static void writel_(uint32_t b, void *addr)
 {
 	write32(addr, b);
-	if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) {
+	if (CONFIG(DEBUG_SPI_FLASH)) {
 		printk(BIOS_DEBUG, "SPI: wrote %8.8x to %4.4x\n",
 				b, (((uint32_t) addr) & SPI_OFFSET_MASK));
 	}