summaryrefslogtreecommitdiff
path: root/src/soc/intel/fsp_baytrail
diff options
context:
space:
mode:
authorElyes HAOUAS <ehaouas@noos.fr>2016-07-29 18:31:16 +0200
committerMartin Roth <martinroth@google.com>2016-07-31 19:27:53 +0200
commit038e7247dc9705ff2d47dd90ec9a807f6feb52ba (patch)
tree8cca6a6db31d20a8e045ee5892e8f9cb8de43f8d /src/soc/intel/fsp_baytrail
parentf9e7d1b0ca7282a0d51313a68f90e9298c0c46c6 (diff)
downloadcoreboot-038e7247dc9705ff2d47dd90ec9a807f6feb52ba.tar.xz
src/soc: Capitalize CPU, ACPI, RAM and ROM
Change-Id: I7f0d3400126d593bad8e78f95e6b9a378463b4ce Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15963 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/fsp_baytrail')
-rw-r--r--src/soc/intel/fsp_baytrail/cpu.c2
-rw-r--r--src/soc/intel/fsp_baytrail/include/soc/iosf.h4
-rw-r--r--src/soc/intel/fsp_baytrail/romstage/romstage.c2
3 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c
index 3fba0b7808..742b2ef794 100644
--- a/src/soc/intel/fsp_baytrail/cpu.c
+++ b/src/soc/intel/fsp_baytrail/cpu.c
@@ -94,7 +94,7 @@ static void pre_mp_init(void)
{
x86_mtrr_check();
- /* Enable the local cpu apics */
+ /* Enable the local CPU apics */
setup_lapic();
}
diff --git a/src/soc/intel/fsp_baytrail/include/soc/iosf.h b/src/soc/intel/fsp_baytrail/include/soc/iosf.h
index a220469cd2..0982da68db 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/iosf.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/iosf.h
@@ -186,11 +186,11 @@ void iosf_ssus_write(int reg, uint32_t val);
#define BNOCACHE 0x23
/* BMBOUND has a 128MiB granularity. Highest address is 0xf8000000. */
#define BUNIT_BMBOUND 0x25
-/* BMBOUND_HI describes the available ram above 4GiB. It has a
+/* BMBOUND_HI describes the available RAM above 4GiB. It has a
* 256MiB granularity. Physical address bits 35:28 are compared with 31:24
* bits in the BMBOUND_HI register. Also note that since BMBOUND has 128MiB
* granularity care needs to be taken with the e820 map to account for a hole
- * in the ram. */
+ * in the RAM. */
#define BUNIT_BMBOUND_HI 0x26
#define BUNIT_MMCONF_REG 0x27
/* The SMMRR registers define the SMM region in MiB granularity. */
diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c
index 881ad0b9b5..a7ed414da8 100644
--- a/src/soc/intel/fsp_baytrail/romstage/romstage.c
+++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c
@@ -244,7 +244,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr)
late_mainboard_romstage_entry();
post_code(0x4c);
- /* if S3 resume skip ram check */
+ /* if S3 resume skip RAM check */
if (prev_sleep_state != ACPI_S3) {
quick_ram_check();
post_code(0x4d);