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| author | Duncan Laurie <dlaurie@chromium.org> | 2017-12-13 13:58:35 -0800 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2017-12-14 22:51:19 +0000 |
| commit | 14485efbb33e417330df59fcc501b336e14ef55c (patch) | |
| tree | 313782948155984f16010c72c9c27cd5009286b0 /src/soc/intel/fsp_baytrail | |
| parent | 6827cb38578ad508e8abdd73cf3eb2306b6effad (diff) | |
| download | coreboot-14485efbb33e417330df59fcc501b336e14ef55c.tar.xz | |
soc/intel/skylake: Add integrated LAN config parameters
Add parameters to configure the integrated LAN via FSP. Since
this takes over a PCI CLKREQ# pin it needs to know which pin
it should use, and there are additional parameters for LTR and
a "K1 power save" feature.
This was tested on a KBL-R board with integrated LAN, verifying
that the device is functional under Linux with the e1000e driver.
Change-Id: Idb200cec90a3c0d4d9c914bae9983a3bcdafcd06
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/22856
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/fsp_baytrail')
0 files changed, 0 insertions, 0 deletions