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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-12-28 15:48:58 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2019-01-06 14:05:20 +0000 |
| commit | adc4753a8d8c5dc7462547ab148c2d63eabbe4fa (patch) | |
| tree | c93ad6be8d24feaa5a04c03a1d434897189be357 /src/soc/intel/fsp_baytrail | |
| parent | 085a2268083cfe1d22f696c9070726dcf2dc160f (diff) | |
| download | coreboot-adc4753a8d8c5dc7462547ab148c2d63eabbe4fa.tar.xz | |
usbdebug: Make the EHCI debug console work in the bootblock
Currently this needlessly initializes the hardware in the both the
romstage and the bootblock, but it works.
Build option is renamed to USBDEBUG_IN_PRE_RAM to reflect the
use better, related support files can be built to pre-ram stages
regardless of usbdebug being enabled or not.
Tested on Google/peppy (adapted to C_ENVIRONMENT_BOOTBLOCK).
Change-Id: Ib77f2fc7f3d8fa524405601bae15cce9f76ffc6f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/fsp_baytrail')
| -rw-r--r-- | src/soc/intel/fsp_baytrail/romstage/romstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index 15ab9ec949..19a0d44ecb 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -227,7 +227,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) __func__, (u32) status, (u32) hob_list_ptr); /* FSP reconfigures USB, so reinit it to have debug */ - if (IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE)) + if (IS_ENABLED(CONFIG_USBDEBUG_IN_PRE_RAM)) usbdebug_hw_init(true); printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status); |