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authorElyes HAOUAS <ehaouas@noos.fr>2018-10-17 10:56:26 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-10-23 15:52:09 +0000
commita342f3937e7ce159fd170ab8cd26ba799a3bc9e4 (patch)
tree4bd4540ba11286f465272c1fbee62dbf5f9789f8 /src/soc/intel/fsp_baytrail
parent9856892297ad997f586a1b4dd0a494f3764a0ce2 (diff)
downloadcoreboot-a342f3937e7ce159fd170ab8cd26ba799a3bc9e4.tar.xz
src: Remove unneeded whitespace
Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel/fsp_baytrail')
-rw-r--r--src/soc/intel/fsp_baytrail/bootblock/bootblock.c4
-rw-r--r--src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c4
-rw-r--r--src/soc/intel/fsp_baytrail/northcluster.c2
3 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c
index 6f0049f9d0..8ce0a1d523 100644
--- a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c
+++ b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c
@@ -37,8 +37,8 @@ static void check_for_warm_reset(void)
* Check if INIT# is asserted by port 0xCF9 and whether RCBA has been set.
* If either is true, then this is a warm reset so execute a Hard Reset
*/
- if ( (inb(0xcf9) == 0x04) ||
- (pci_io_read_config32(LPC_BDF, RCBA) & RCBA_ENABLE) ) {
+ if ((inb(0xcf9) == 0x04) ||
+ (pci_io_read_config32(LPC_BDF, RCBA) & RCBA_ENABLE)) {
outb(0x00, 0xcf9);
outb(0x06, 0xcf9);
}
diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
index c5863f459f..13bc883781 100644
--- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
+++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
@@ -314,7 +314,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams,
if (prev_sleep_state == ACPI_S3) {
/* S3 resume */
- if ( pFspInitParams->NvsBufferPtr == NULL) {
+ if (pFspInitParams->NvsBufferPtr == NULL) {
/* If waking from S3 and no cache then. */
printk(BIOS_WARNING, "No MRC cache found in S3 resume path.\n");
post_code(POST_RESUME_FAILURE);
@@ -322,7 +322,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams,
outl(inl(ACPI_BASE_ADDRESS + PM1_CNT) &
~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
/* Reboot */
- printk(BIOS_WARNING,"Rebooting..\n" );
+ printk(BIOS_WARNING, "Rebooting..\n" );
system_reset();
/* Should not reach here.. */
die("Reboot System\n");
diff --git a/src/soc/intel/fsp_baytrail/northcluster.c b/src/soc/intel/fsp_baytrail/northcluster.c
index 9f22b25a5d..f909121eb2 100644
--- a/src/soc/intel/fsp_baytrail/northcluster.c
+++ b/src/soc/intel/fsp_baytrail/northcluster.c
@@ -158,7 +158,7 @@ static void mc_add_dram_resources(struct device *dev)
(bmbound - fsp_mem_base) >> 10);
if (highmem_size) {
- ram_resource(dev, index++, 0x100000000 >> 10, highmem_size >> 10 );
+ ram_resource(dev, index++, 0x100000000 >> 10, highmem_size >> 10);
}
printk(BIOS_INFO, "Available memory above 4GB: %lluM\n",
highmem_size >> 20);