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author | Andrey Petrov <anpetrov@fb.com> | 2019-09-10 20:32:56 -0700 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-09-24 10:29:58 +0000 |
commit | 2fa4938796bb000a273f6935db139de64e200712 (patch) | |
tree | f4696a5adf1bd4701d4c3e9dab5c88b32b1a3f75 /src/soc/intel/fsp_broadwell_de/Makefile.inc | |
parent | 8dc95ddbd4a9354eec124393f996a36c3a7329e2 (diff) | |
download | coreboot-2fa4938796bb000a273f6935db139de64e200712.tar.xz |
soc/fsp_broadwell_de: Add devhide functionality
Add function to hide IIO PCIe root ports.
TEST=On OCP Monolake, hide built-in NIC PCIe root port [0.2.2 and 0.2.3]
and make sure OS does not detect built-in NIC.
Change-Id: I2fcac5b7d9a7a52a2801c010bfccf247f2a44581
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/soc/intel/fsp_broadwell_de/Makefile.inc')
-rw-r--r-- | src/soc/intel/fsp_broadwell_de/Makefile.inc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/fsp_broadwell_de/Makefile.inc b/src/soc/intel/fsp_broadwell_de/Makefile.inc index 70cb2de6ed..7b8a788c19 100644 --- a/src/soc/intel/fsp_broadwell_de/Makefile.inc +++ b/src/soc/intel/fsp_broadwell_de/Makefile.inc @@ -15,6 +15,7 @@ romstage-y += gpio.c romstage-y += memmap.c romstage-y += tsc_freq.c romstage-y += smbus-imc.c +romstage-y += ubox.c postcar-y += tsc_freq.c @@ -32,6 +33,7 @@ ramstage-y += smi.c ramstage-y += southcluster.c ramstage-y += tsc_freq.c ramstage-y += vtd.c +ramstage-y += ubox.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c |