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| author | Werner Zeh <werner.zeh@siemens.com> | 2018-04-05 07:41:52 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-04-06 07:02:54 +0000 |
| commit | cacc5a3eb035eed278a2d1eec76f14c55b0b7211 (patch) | |
| tree | b7382adb184bde607a27979cdb5cb1f2e7a82c1e /src/soc/intel/fsp_broadwell_de/fsp | |
| parent | 3caf34167c0d05f53bf1b466117ff234f5c7e14e (diff) | |
| download | coreboot-cacc5a3eb035eed278a2d1eec76f14c55b0b7211.tar.xz | |
fsp_broadwell_de: Provide valid address and size for DCACHE range
On Broadwell-DE the FSP sets up DCACHE in the early call. The address
does not match the default FSP 1.0 address defined in
src/drivers/intel/fsp1_0/Kconfig which leads to errors when this range
is used in pre-ramstage stages.
This patch provides the matching DCACHE_RAM_BASE value among with a
suitable DCACHE_RAM_SIZE for the FSP based Broadwell-DE implementation.
The include order of Kconfig files makes sure that the Kconfig file in
the soc directory is sourced first and the defined values will override
the ones in src/drivers/intel/fsp1_0/Kconfig.
Change-Id: I2a55b576541a3d974ee2714b198095aa24fc46f5
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/25535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/fsp_broadwell_de/fsp')
| -rw-r--r-- | src/soc/intel/fsp_broadwell_de/fsp/Kconfig | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/soc/intel/fsp_broadwell_de/fsp/Kconfig b/src/soc/intel/fsp_broadwell_de/fsp/Kconfig index 2e1ebebd44..e9c6c312e6 100644 --- a/src/soc/intel/fsp_broadwell_de/fsp/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/fsp/Kconfig @@ -21,6 +21,22 @@ config FSP_LOC The Broadwell-DE FSP is built with a preferred base address of 0xffeb0000. +config DCACHE_RAM_BASE + hex + default 0xfe100000 + help + This address needs to match the setup performed inside FSP. + On Broadwell-DE the FSP allocates temporary RAM starting at 0xfe100000. + +config DCACHE_RAM_SIZE + hex + default 0x8000 + help + The DCACHE is shared between FSP itself and the rest of the coreboot + stages. A size of 0x8000 works fine while providing enough space for + features like VBOOT in verstage. Further increase to a power of two + aligned value leads to errors in FSP. + config FSP_MEMORY_DOWN bool "Enable Memory Down" default n |