diff options
author | Werner Zeh <werner.zeh@siemens.com> | 2017-04-06 10:01:24 +0200 |
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committer | Werner Zeh <werner.zeh@siemens.com> | 2017-04-28 06:19:20 +0200 |
commit | 97c0979befedb822e9d77bc0e11374e291332c49 (patch) | |
tree | bafd0c0ef23af3e1bf22da14cd47655ee5f5ed2e /src/soc/intel/fsp_broadwell_de/smi.c | |
parent | 00d250e2289de2e39ab6f69a61176405cdfa9ddb (diff) | |
download | coreboot-97c0979befedb822e9d77bc0e11374e291332c49.tar.xz |
fsp_broadwell_de: Add SMM code
Add basic SMM support for Broadwell-DE SoC.
The code is mainly based on the SMM implementation of Broadwell with a
few differences:
- EMRR is now called PRMRR and the UNCORE part of it is not available
- SMM_FEATURE_CONTROL is no longer a MSR but is now located in PCI space
- currently only SERIRQ-SMI has a handler
Change-Id: I461a14d411aedefdb0cb54ae43b91103a80a4f6a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/19145
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/fsp_broadwell_de/smi.c')
-rw-r--r-- | src/soc/intel/fsp_broadwell_de/smi.c | 87 |
1 files changed, 87 insertions, 0 deletions
diff --git a/src/soc/intel/fsp_broadwell_de/smi.c b/src/soc/intel/fsp_broadwell_de/smi.c new file mode 100644 index 0000000000..5411bcaed0 --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/smi.c @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2017 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <arch/io.h> +#include <soc/iomap.h> +#include <soc/lpc.h> +#include <soc/smm.h> + +void southbridge_smm_clear_state(void) +{ + u32 smi_en; + + printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); + printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", ACPI_BASE_ADDRESS); + + smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN); + if (smi_en & APMC_EN) { + printk(BIOS_INFO, "SMI# handler already enabled?\n"); + return; + } + + printk(BIOS_DEBUG, "\n"); + + /* Dump and clear status registers */ + clear_smi_status(); + clear_pm1_status(); +} + +void southbridge_smm_enable_smi(void) +{ + printk(BIOS_DEBUG, "Enabling SMIs.\n"); + + /* Clear all possible set SMI status bits + before enabling SMIs. */ + southbridge_clear_smi_status(); + + /* Enable SMI generation: + - on SERIRQ-SMI (is always enabled) */ + enable_smi(EOS | GBL_SMI_EN); +} + +void southbridge_trigger_smi(void) +{ + /* + * There are several methods of raising a controlled SMI# via + * software, among them: + * - Writes to io 0xb2 (APMC) + * - Writes to the Local Apic ICR with Delivery mode SMI. + * + * Using the local apic is a bit more tricky. According to + * AMD Family 11 Processor BKDG no destination shorthand must be + * used. + * The whole SMM initialization is quite a bit hardware specific, so + * I'm not too worried about the better of the methods at the moment + */ + + /* Raise an SMI interrupt */ + printk(BIOS_SPEW, " ... raise SMI#\n"); + outb(0x00, 0xb2); +} + +void southbridge_clear_smi_status(void) +{ + /* Clear SMI status */ + clear_smi_status(); + + /* Clear PM1 status */ + clear_pm1_status(); + + /* Set EOS bit so other SMIs can occur. */ + enable_smi(EOS); +} |