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author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-19 18:50:20 +0100 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-11-21 06:43:29 +0000 |
commit | f67c81fc7030e278cf3dbc906f9ba5e265d843f0 (patch) | |
tree | c89f4856690b80e8aa3c53a51ff2e4dfd553c84f /src/soc/intel/fsp_broadwell_de/smi.c | |
parent | 433471244b7313dde6bb07d58943bfd0d9957c59 (diff) | |
download | coreboot-f67c81fc7030e278cf3dbc906f9ba5e265d843f0.tar.xz |
soc/intel/fsp_broadwell_de: Drop support
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.
Change-Id: I8b6502b0894f9e2b8b1334871d7b6cde65cba7d4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/soc/intel/fsp_broadwell_de/smi.c')
-rw-r--r-- | src/soc/intel/fsp_broadwell_de/smi.c | 90 |
1 files changed, 0 insertions, 90 deletions
diff --git a/src/soc/intel/fsp_broadwell_de/smi.c b/src/soc/intel/fsp_broadwell_de/smi.c deleted file mode 100644 index 299ba531c5..0000000000 --- a/src/soc/intel/fsp_broadwell_de/smi.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <cpu/intel/smm_reloc.h> -#include <arch/io.h> -#include <soc/iomap.h> -#include <soc/lpc.h> -#include <soc/smm.h> - -void smm_southbridge_clear_state(void) -{ - u32 smi_en; - - printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); - printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", ACPI_BASE_ADDRESS); - - smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN); - if (smi_en & APMC_EN) { - printk(BIOS_INFO, "SMI# handler already enabled?\n"); - return; - } - - printk(BIOS_DEBUG, "\n"); - - /* Dump and clear status registers */ - clear_smi_status(); - clear_pm1_status(); -} - -static void southbridge_clear_smi_status(void); - -void smm_southbridge_enable_smi(void) -{ - printk(BIOS_DEBUG, "Enabling SMIs.\n"); - - /* Clear all possible set SMI status bits - before enabling SMIs. */ - southbridge_clear_smi_status(); - - /* Enable SMI generation: - - on SERIRQ-SMI (is always enabled) */ - enable_smi(EOS | GBL_SMI_EN); -} - -static void __unused southbridge_trigger_smi(void) -{ - /* - * There are several methods of raising a controlled SMI# via - * software, among them: - * - Writes to io 0xb2 (APMC) - * - Writes to the Local Apic ICR with Delivery mode SMI. - * - * Using the local apic is a bit more tricky. According to - * AMD Family 11 Processor BKDG no destination shorthand must be - * used. - * The whole SMM initialization is quite a bit hardware specific, so - * I'm not too worried about the better of the methods at the moment - */ - - /* Raise an SMI interrupt */ - printk(BIOS_SPEW, " ... raise SMI#\n"); - outb(0x00, 0xb2); -} - -static void southbridge_clear_smi_status(void) -{ - /* Clear SMI status */ - clear_smi_status(); - - /* Clear PM1 status */ - clear_pm1_status(); - - /* Set EOS bit so other SMIs can occur. */ - enable_smi(EOS); -} |