diff options
| author | Andrey Petrov <anpetrov@fb.com> | 2019-09-10 20:32:56 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-09-24 10:29:58 +0000 |
| commit | 2fa4938796bb000a273f6935db139de64e200712 (patch) | |
| tree | f4696a5adf1bd4701d4c3e9dab5c88b32b1a3f75 /src/soc/intel/fsp_broadwell_de/southcluster.c | |
| parent | 8dc95ddbd4a9354eec124393f996a36c3a7329e2 (diff) | |
| download | coreboot-2fa4938796bb000a273f6935db139de64e200712.tar.xz | |
soc/fsp_broadwell_de: Add devhide functionality
Add function to hide IIO PCIe root ports.
TEST=On OCP Monolake, hide built-in NIC PCIe root port [0.2.2 and 0.2.3]
and make sure OS does not detect built-in NIC.
Change-Id: I2fcac5b7d9a7a52a2801c010bfccf247f2a44581
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/soc/intel/fsp_broadwell_de/southcluster.c')
| -rw-r--r-- | src/soc/intel/fsp_broadwell_de/southcluster.c | 24 |
1 files changed, 19 insertions, 5 deletions
diff --git a/src/soc/intel/fsp_broadwell_de/southcluster.c b/src/soc/intel/fsp_broadwell_de/southcluster.c index 599b8c5e7f..cb52e56e8a 100644 --- a/src/soc/intel/fsp_broadwell_de/southcluster.c +++ b/src/soc/intel/fsp_broadwell_de/southcluster.c @@ -33,6 +33,7 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/acpi.h> +#include <soc/ubox.h> #include "chip.h" typedef struct soc_intel_fsp_broadwell_de_config config_t; @@ -250,12 +251,25 @@ void southcluster_enable_dev(struct device *dev) { uint32_t reg32; - if (!dev->enabled) { - int slot = PCI_SLOT(dev->path.pci.devfn); - int func = PCI_FUNC(dev->path.pci.devfn); - printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n", - dev_path(dev), slot, func); + if (dev->enabled) + return; + const int slot = PCI_SLOT(dev->path.pci.devfn); + const int func = PCI_FUNC(dev->path.pci.devfn); + + switch (slot) { + case PCIE_IIO_PORT_0_DEV: + die("should not hide PCH link"); + case PCIE_IIO_PORT_1_DEV: /* fallthrough */ + case PCIE_IIO_PORT_2_DEV: /* fallthrough */ + case PCIE_IIO_PORT_3_DEV: /* fallthrough */ + printk(BIOS_DEBUG, "%s: Disabling IOU bridge %02x.%01x\n", dev_path(dev), slot, + func); + iio_hide(slot, func); + break; + default: + printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n", dev_path(dev), slot, + func); /* Ensure memory, io, and bus master are all disabled */ reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |