diff options
| author | Werner Zeh <werner.zeh@siemens.com> | 2017-10-16 08:37:28 +0200 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-19 15:13:40 +0000 |
| commit | 4bf11ce2b5de81ec0bd6799f4830a48c7376c122 (patch) | |
| tree | d2e34db2f81666fcd969930a2f2565e8e64cc045 /src/soc/intel/fsp_broadwell_de/southcluster.c | |
| parent | e77d588ee46bfdff1a152f166eca84e3c5827665 (diff) | |
| download | coreboot-4bf11ce2b5de81ec0bd6799f4830a48c7376c122.tar.xz | |
soc/fsp_broadwell_de: Add support for GPIO handling
Add functionality to initialize, set and read back GPIOs on FSP based
Broadwell-DE implementation.
Change-Id: Ibbd86e2142bbf5772eb4a91ebb9166c31d52476e
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/22034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/fsp_broadwell_de/southcluster.c')
| -rw-r--r-- | src/soc/intel/fsp_broadwell_de/southcluster.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/intel/fsp_broadwell_de/southcluster.c b/src/soc/intel/fsp_broadwell_de/southcluster.c index e8c8706a5c..3bf5429e39 100644 --- a/src/soc/intel/fsp_broadwell_de/southcluster.c +++ b/src/soc/intel/fsp_broadwell_de/southcluster.c @@ -4,6 +4,7 @@ * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2013 Google Inc. * Copyright (C) 2015-2016 Intel Corp. + * Copyright (C) 2017 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -196,6 +197,17 @@ static void sc_add_io_resources(device_t dev) res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER; res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + /* Add the resource for GPIOs */ + res = new_resource(dev, GPIO_BASE_ADR_OFFSET); + res->base = GPIO_BASE_ADDRESS; + res->size = GPIO_BASE_SIZE; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + /* There is a separated enable-bit in GPIO_CTRL-register. It was set + * already in romstage but FSP was active in the meantime and could have + * cleared it. Set it here again to enable allocated IO-space for sure. + */ + pci_write_config8(dev, GPIO_CTRL_OFFSET, GPIO_DECODE_ENABLE); } static void sc_read_resources(device_t dev) |