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| author | Werner Zeh <werner.zeh@siemens.com> | 2016-09-08 07:27:29 +0200 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2016-09-12 06:33:53 +0200 |
| commit | 91aea428b5932c031b81a6c4921ac416f2b2c995 (patch) | |
| tree | 4290e161963bfc1ca1f31d3d668b619a90ded5ca /src/soc/intel/fsp_broadwell_de | |
| parent | ba349ab12eb5c6848d7e3b727d6fcd7fbe616614 (diff) | |
| download | coreboot-91aea428b5932c031b81a6c4921ac416f2b2c995.tar.xz | |
fsp_broadwell_de: Correct access to SIRQ_CNTL register
The serial IRQ configuration register is only 8 bit wide so switch the
PCI access from 16 bits to 8 bits.
Change-Id: Ia9fbc02251e00b31440bf103e2afc2ff285b7f2e
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/16534
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/fsp_broadwell_de')
| -rw-r--r-- | src/soc/intel/fsp_broadwell_de/southcluster.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/fsp_broadwell_de/southcluster.c b/src/soc/intel/fsp_broadwell_de/southcluster.c index 7024814bb2..7ed889662e 100644 --- a/src/soc/intel/fsp_broadwell_de/southcluster.c +++ b/src/soc/intel/fsp_broadwell_de/southcluster.c @@ -215,7 +215,7 @@ static void sc_init(struct device *dev) PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); /* Program Serial IRQ register. */ - pci_write_config16(dev, 0x64, 0xd0); + pci_write_config8(dev, 0x64, 0xd0); sc_pirq_init(dev); write_pci_config_irqs(); |