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| author | Werner Zeh <werner.zeh@siemens.com> | 2016-07-06 12:58:57 +0200 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2016-07-07 06:19:33 +0200 |
| commit | 93db5a5eeea78423ca763bff013d3610655e3776 (patch) | |
| tree | 6146ce45c2c9c2f86e1b72c3a4f3e466dfbf78f4 /src/soc/intel/fsp_broadwell_de | |
| parent | 2566f9173d478b25275a1afbbd792634902a52c4 (diff) | |
| download | coreboot-93db5a5eeea78423ca763bff013d3610655e3776.tar.xz | |
intel/fsp_broadwell_de: Do not use hard coded SCI IRQ for ACPI
The SCI interrupt can be routed to different IRQs using ACPI control
register. Instead of using hard coded IRQ9 for ACPI table generation
read back the register and return the used IRQ number. This way SCI IRQ
can be modified (e.g. for a given mainboard) and ACPI tables will
remain consistent.
Change-Id: I534fc69eb1df28cd8d733d1ac6b2081d2dcf7511
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/15548
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: York Yang <york.yang@intel.com>
Diffstat (limited to 'src/soc/intel/fsp_broadwell_de')
| -rw-r--r-- | src/soc/intel/fsp_broadwell_de/acpi.c | 30 | ||||
| -rw-r--r-- | src/soc/intel/fsp_broadwell_de/include/soc/irq.h | 10 |
2 files changed, 39 insertions, 1 deletions
diff --git a/src/soc/intel/fsp_broadwell_de/acpi.c b/src/soc/intel/fsp_broadwell_de/acpi.c index afa4048f09..1e088684c0 100644 --- a/src/soc/intel/fsp_broadwell_de/acpi.c +++ b/src/soc/intel/fsp_broadwell_de/acpi.c @@ -78,7 +78,35 @@ static acpi_cstate_t cstate_map[] = { static int acpi_sci_irq(void) { - return 9; + uint8_t actl = 0; + static uint8_t sci_irq = 0; + device_t dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + + /* If this function was already called, just return the stored value. */ + if (sci_irq) + return sci_irq; + /* Get contents of ACPI control register. */ + actl = pci_read_config8(dev, ACPI_CNTL_OFFSET) & SCIS_MASK; + /* Determine how SCI is routed. */ + switch (actl) { + case SCIS_IRQ9: + case SCIS_IRQ10: + case SCIS_IRQ11: + sci_irq = actl + 9; + break; + case SCIS_IRQ20: + case SCIS_IRQ21: + case SCIS_IRQ22: + case SCIS_IRQ23: + sci_irq = actl - SCIS_IRQ20 + 20; + break; + default: + printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n"); + sci_irq = 9; + break; + } + printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq); + return sci_irq; } void acpi_create_intel_hpet(acpi_hpet_t *hpet) diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/irq.h b/src/soc/intel/fsp_broadwell_de/include/soc/irq.h index ea043267e3..1344f3b880 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/irq.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/irq.h @@ -51,6 +51,16 @@ #define PIRQG 6 #define PIRQH 7 +#define ACPI_CNTL_OFFSET 0x44 +#define SCIS_MASK 0x07 +#define SCIS_IRQ9 0x00 +#define SCIS_IRQ10 0x01 +#define SCIS_IRQ11 0x02 +#define SCIS_IRQ20 0x04 +#define SCIS_IRQ21 0x05 +#define SCIS_IRQ22 0x06 +#define SCIS_IRQ23 0x07 + /* In each mainboard directory there should exist a header file irqroute.h that * defines the PCI_DEV_PIRQ_ROUTES and PIRQ_PIC_ROUTES macros which * consist of PCI_DEV_PIRQ_ROUTE and PIRQ_PIC entries. */ |