summaryrefslogtreecommitdiff
path: root/src/soc/intel/icelake/Kconfig
diff options
context:
space:
mode:
authorSubrata Banik <subrata.banik@intel.com>2018-11-20 13:20:31 +0530
committerSubrata Banik <subrata.banik@intel.com>2018-11-22 02:26:33 +0000
commit26d706bb333827c983abf7d734ce5af621d7adeb (patch)
tree186347a0a9e64b0e0b2b474f8fe5148b856ce417 /src/soc/intel/icelake/Kconfig
parentdd4ef173f1082f670ad6302bf93d37cc57f8b043 (diff)
downloadcoreboot-26d706bb333827c983abf7d734ce5af621d7adeb.tar.xz
soc/intel/icelake: Create macros for FSP consumption
1. Modify PCIEXBAR to accomodate Type-C Root Port 2. LPSS device mode selection Change-Id: Ib7e4bc304f93e4b63ac2d7f194ca441dd96dd943 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/29697 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/icelake/Kconfig')
-rw-r--r--src/soc/intel/icelake/Kconfig8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig
index c4ee841802..727fccee0f 100644
--- a/src/soc/intel/icelake/Kconfig
+++ b/src/soc/intel/icelake/Kconfig
@@ -126,6 +126,10 @@ config PCR_BASE_ADDRESS
help
This option allows you to select MMIO Base Address of sideband bus.
+config MMCONF_BASE_ADDRESS
+ hex
+ default 0xc0000000
+
config CPU_BCLK_MHZ
int
default 100
@@ -146,6 +150,10 @@ config SOC_INTEL_I2C_DEV_MAX
int
default 6
+config SOC_INTEL_UART_DEV_MAX
+ int
+ default 3
+
# Clock divider parameters for 115200 baud rate
config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
hex