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| author | Nico Huber <nico.h@gmx.de> | 2018-11-11 02:51:14 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-01-09 22:15:48 +0000 |
| commit | a96e66a76f21c41b0c15db8d9df1d721f4a8a9af (patch) | |
| tree | 6cc4301dec4b2ca50a7c0fb43f92c60706bc7e14 /src/soc/intel/icelake/Kconfig | |
| parent | 3910c4e4882876d70dfef08c6cc3946bc190d9ed (diff) | |
| download | coreboot-a96e66a76f21c41b0c15db8d9df1d721f4a8a9af.tar.xz | |
soc/intel: Clean mess around UART_DEBUG
Everything is wrong here, the Kconfig symbols are only the tip of the
iceberg. Based on Kconfig prompts the SoC code performed pad configu-
rations! I don't see why the person who configures coreboot should have
the board schematics at hand.
As a mitigation, we remove the prompts for UART_DEBUG, which is renamed
to INTEL_LPSS_UART_FOR_CONSOLE (because the former didn't really say
what it's about), and for UART_FOR_CONSOLE in case the former is selec-
ted.
Change-Id: Ibe2ed3cab0bb04bb23989c22da45299f088c758b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc/intel/icelake/Kconfig')
| -rw-r--r-- | src/soc/intel/icelake/Kconfig | 17 |
1 files changed, 0 insertions, 17 deletions
diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 6343ca5d0f..1d687f0224 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -62,23 +62,6 @@ config CPU_SPECIFIC_OPTIONS select UDK_2017_BINDING select DISPLAY_FSP_VERSION_INFO -config UART_DEBUG - bool "Enable UART debug port." - default n - select CONSOLE_SERIAL - select BOOTBLOCK_CONSOLE - select DRIVERS_UART - select DRIVERS_UART_8250MEM_32 - select NO_UART_ON_SUPERIO - -config UART_FOR_CONSOLE - int "Index for LPSS UART port to use for console" - default 2 if DRIVERS_UART_8250MEM_32 - default 0 - help - Index for LPSS UART port to use for console: - 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2 - config DCACHE_RAM_BASE default 0xfef00000 |