diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2020-02-25 10:29:15 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-02-26 02:21:46 +0000 |
| commit | 646109a4ea12b28ec5c5cd89c4066bb37835605f (patch) | |
| tree | 70d06507747ec05e5c2fc771fbd156a05b0fd859 /src/soc/intel/icelake/fsp_params.c | |
| parent | e53f8c902535bf979f9549e09d5ecf4b8d922019 (diff) | |
| download | coreboot-646109a4ea12b28ec5c5cd89c4066bb37835605f.tar.xz | |
soc/intel/{cnl,icl}: Avoid static 8254 clock gating on S3 resume
This patch makes all legacy 8254 FSP UPDs (Enable8254ClockGating and
Enable8254ClockGatingOnS3) depend on CONFIG_USE_LEGACY_8254_TIMER to
avoid discrepancy between S0 and S3 resume flow.
TEST=Able to boot to TianoCore without any hangs and errors, also
verified S3 resume path doesn't clock gate 8254 timer using FSP-S UPD.
Change-Id: Id6fe74a51537abbb9ff48db925e37a64e5b21f78
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39110
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/icelake/fsp_params.c')
| -rw-r--r-- | src/soc/intel/icelake/fsp_params.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index 7514be107d..334fac8766 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -140,7 +140,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Legacy 8254 timer support */ params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; - params->Enable8254ClockGatingOnS3 = 1; + params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER; /* S0ix */ params->PchPmSlpS0Enable = config->s0ix_enable; |