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authorSubrata Banik <subrata.banik@intel.com>2019-11-05 16:54:58 +0530
committerPatrick Georgi <pgeorgi@google.com>2019-11-07 14:14:11 +0000
commit1b1a26acdc814d0478bb5fda0b6664076a60fdf1 (patch)
tree50add962d32b07ff52ab40e166f2bf078fabd82f /src/soc/intel/icelake/include
parent114e2e88305a6e1fc972a58a03b89a23685e5a48 (diff)
downloadcoreboot-1b1a26acdc814d0478bb5fda0b6664076a60fdf1.tar.xz
soc/intel/icelake: Refactor pch_early_init() code
This patch keeps required pch_early_init() function like ABASE programming, GPE and RTC init into bootblock and moves remaining functions like TCO configuration and SMBUS init into romstage/pch.c in order to maintain only required chipset programming for bootblock and verstage. TEST=Able to build and boot ICL DE system. Change-Id: I4f0914242c3215f6bf76e41c468f544361a740d8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36627 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/icelake/include')
-rw-r--r--src/soc/intel/icelake/include/soc/romstage.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/icelake/include/soc/romstage.h b/src/soc/intel/icelake/include/soc/romstage.h
index e931811302..977c7c057a 100644
--- a/src/soc/intel/icelake/include/soc/romstage.h
+++ b/src/soc/intel/icelake/include/soc/romstage.h
@@ -20,6 +20,7 @@
void mainboard_memory_init_params(FSPM_UPD *mupd);
void systemagent_early_init(void);
+void pch_init(void);
/* Board type */
enum board_type {