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authorSubrata Banik <subrata.banik@intel.com>2019-10-30 15:47:06 +0530
committerPatrick Georgi <pgeorgi@google.com>2019-11-01 11:50:31 +0000
commitfa2f793957d03c96b2ad3a048b0889fe4203cb81 (patch)
treec5e8c383dbebcd05a47f9546197d085208400bc6 /src/soc/intel/icelake/include
parent2715cdb3f32fcebdd1de6870a665a2b613c07e60 (diff)
downloadcoreboot-fa2f793957d03c96b2ad3a048b0889fe4203cb81.tar.xz
soc/intel/{cnl,icl}: Move globalnvs.asl/nvs.h into common/block/
This patch creates a common instance of globalnvs.asl/nvs.h inside intel common code (soc/intel/common/block/) and ask cnl & icl soc code to refer globalnvs.asl and nvs.h from common code block. TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify GNVS operation region presence after booting to OS. Change-Id: Ia9fb12a75557bd7dc38f6d22ba2b32065d18b3ee Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/icelake/include')
-rw-r--r--src/soc/intel/icelake/include/soc/nvs.h30
1 files changed, 1 insertions, 29 deletions
diff --git a/src/soc/intel/icelake/include/soc/nvs.h b/src/soc/intel/icelake/include/soc/nvs.h
index b2d903a4f5..c855df0305 100644
--- a/src/soc/intel/icelake/include/soc/nvs.h
+++ b/src/soc/intel/icelake/include/soc/nvs.h
@@ -16,34 +16,6 @@
#ifndef _SOC_NVS_H_
#define _SOC_NVS_H_
-#include <commonlib/helpers.h>
-#include <vendorcode/google/chromeos/gnvs.h>
-
-typedef struct global_nvs_t {
- /* Miscellaneous */
- u16 osys; /* 0x00 - 0x01 Operating System */
- u8 smif; /* 0x02 - SMI function call ("TRAP") */
- u8 pcnt; /* 0x03 - Processor Count */
- u8 ppcm; /* 0x04 - Max PPC State */
- u8 tlvl; /* 0x05 - Throttle Level Limit */
- u8 lids; /* 0x06 - LID State */
- u8 pwrs; /* 0x07 - AC Power State */
- u32 cbmc; /* 0x08 - 0xb AC Power State */
- u64 pm1i; /* 0x0c - 0x13 PM1 wake status bit */
- u64 gpei; /* 0x14 - 0x1b GPE wake status bit */
- u8 dpte; /* 0x1c - Enable DPTF */
- u64 nhla; /* 0x1d - 0x24 NHLT Address */
- u32 nhll; /* 0x25 - 0x28 NHLT Length */
- u16 cid1; /* 0x29 - 0x2a Wifi Country Identifier */
- u16 u2we; /* 0x2b - 0x2c USB2 Wake Enable Bitmap */
- u16 u3we; /* 0x2d - 0x2e USB3 Wake Enable Bitmap */
- u8 uior; /* 0x2f - UART debug controller init on S3 resume */
- u8 unused[208];
-
- /* ChromeOS specific (0x100 - 0xfff) */
- chromeos_acpi_t chromeos;
-} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
-
+#include <intelblocks/nvs.h>
#endif