summaryrefslogtreecommitdiff
path: root/src/soc/intel/icelake/memmap.c
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-16 10:37:15 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-28 22:48:00 +0000
commit81100bf7ff62c4ee53214afb82f2fa9112d109b6 (patch)
tree8fdb92df42e60e200095aac64eb6b9781c54594f /src/soc/intel/icelake/memmap.c
parent4007d7f8c73d2872c6fe74f2b58a673161d6c947 (diff)
downloadcoreboot-81100bf7ff62c4ee53214afb82f2fa9112d109b6.tar.xz
soc/intel: Move fill_postcar_frame to memmap.c
Change-Id: I84b1fad52d623a879f00c3f721f480f58d7d6d8a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34894 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/icelake/memmap.c')
-rw-r--r--src/soc/intel/icelake/memmap.c17
1 files changed, 17 insertions, 0 deletions
diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c
index 0d41f25280..71368c645a 100644
--- a/src/soc/intel/icelake/memmap.c
+++ b/src/soc/intel/icelake/memmap.c
@@ -13,9 +13,11 @@
* GNU General Public License for more details.
*/
+#include <arch/romstage.h>
#include <arch/ebda.h>
#include <cbmem.h>
#include <console/console.h>
+#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <device/device.h>
#include <device/pci.h>
@@ -262,3 +264,18 @@ void *cbmem_top(void)
return (void *)(uintptr_t)ebda_cfg.tolum_base;
}
+
+void fill_postcar_frame(struct postcar_frame *pcf)
+{
+ uintptr_t top_of_ram;
+ /*
+ * We need to make sure ramstage will be run cached. At this
+ * point exact location of ramstage in cbmem is not known.
+ * Instruct postcar to cache 16 megs under cbmem top which is
+ * a safe bet to cover ramstage.
+ */
+ top_of_ram = (uintptr_t) cbmem_top();
+ printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
+ top_of_ram -= 16*MiB;
+ postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
+}