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author | Wonkyu Kim <wonkyu.kim@intel.com> | 2020-03-12 18:35:35 -0700 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-15 12:56:21 +0000 |
commit | 655dba40559e79fcac520a51819d10cd58c25adf (patch) | |
tree | 935168e82aa81625155b483adfdd4323636e9f72 /src/soc/intel/icelake/romstage/fsp_params.c | |
parent | 4d5fd77cf82e95b74c80790389c3616de2b81411 (diff) | |
download | coreboot-655dba40559e79fcac520a51819d10cd58c25adf.tar.xz |
soc/intel/tigerlake: Match RP number with TGL EDS
Update RP number to 12 according to PCH EDS#576591 vol1 rev1.2.
BUG=b:151208838
TEST=build RVP successfully
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Iabdbfd99f7154741c16da53bcd9d1c7ca4f81129
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Diffstat (limited to 'src/soc/intel/icelake/romstage/fsp_params.c')
0 files changed, 0 insertions, 0 deletions