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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-16 10:37:15 +0300 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-28 22:48:00 +0000 |
commit | 81100bf7ff62c4ee53214afb82f2fa9112d109b6 (patch) | |
tree | 8fdb92df42e60e200095aac64eb6b9781c54594f /src/soc/intel/icelake/romstage/romstage.c | |
parent | 4007d7f8c73d2872c6fe74f2b58a673161d6c947 (diff) | |
download | coreboot-81100bf7ff62c4ee53214afb82f2fa9112d109b6.tar.xz |
soc/intel: Move fill_postcar_frame to memmap.c
Change-Id: I84b1fad52d623a879f00c3f721f480f58d7d6d8a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34894
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/icelake/romstage/romstage.c')
-rw-r--r-- | src/soc/intel/icelake/romstage/romstage.c | 16 |
1 files changed, 0 insertions, 16 deletions
diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index a96f057d58..3d21a45e33 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -14,7 +14,6 @@ */ #include <arch/romstage.h> -#include <cpu/x86/mtrr.h> #include <cbmem.h> #include <console/console.h> #include <fsp/util.h> @@ -126,18 +125,3 @@ void mainboard_romstage_entry(void) if (!s3wake) save_dimm_info(); } - -void fill_postcar_frame(struct postcar_frame *pcf) -{ - uintptr_t top_of_ram; - /* - * We need to make sure ramstage will be run cached. At this - * point exact location of ramstage in cbmem is not known. - * Instruct postcar to cache 16 megs under cbmem top which is - * a safe bet to cover ramstage. - */ - top_of_ram = (uintptr_t) cbmem_top(); - printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); - top_of_ram -= 16*MiB; - postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); -} |