diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2019-11-05 16:54:58 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-07 14:14:11 +0000 |
| commit | 1b1a26acdc814d0478bb5fda0b6664076a60fdf1 (patch) | |
| tree | 50add962d32b07ff52ab40e166f2bf078fabd82f /src/soc/intel/icelake/romstage | |
| parent | 114e2e88305a6e1fc972a58a03b89a23685e5a48 (diff) | |
| download | coreboot-1b1a26acdc814d0478bb5fda0b6664076a60fdf1.tar.xz | |
soc/intel/icelake: Refactor pch_early_init() code
This patch keeps required pch_early_init() function like ABASE programming,
GPE and RTC init into bootblock and moves remaining functions like
TCO configuration and SMBUS init into romstage/pch.c in order to maintain
only required chipset programming for bootblock and verstage.
TEST=Able to build and boot ICL DE system.
Change-Id: I4f0914242c3215f6bf76e41c468f544361a740d8
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36627
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/icelake/romstage')
| -rw-r--r-- | src/soc/intel/icelake/romstage/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/intel/icelake/romstage/pch.c | 27 | ||||
| -rw-r--r-- | src/soc/intel/icelake/romstage/romstage.c | 2 |
3 files changed, 30 insertions, 0 deletions
diff --git a/src/soc/intel/icelake/romstage/Makefile.inc b/src/soc/intel/icelake/romstage/Makefile.inc index baa4d46e55..b42f3f4b7a 100644 --- a/src/soc/intel/icelake/romstage/Makefile.inc +++ b/src/soc/intel/icelake/romstage/Makefile.inc @@ -16,4 +16,5 @@ romstage-y += fsp_params.c romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c +romstage-y += pch.c romstage-y += systemagent.c diff --git a/src/soc/intel/icelake/romstage/pch.c b/src/soc/intel/icelake/romstage/pch.c new file mode 100644 index 0000000000..88a7cc7163 --- /dev/null +++ b/src/soc/intel/icelake/romstage/pch.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intelblocks/smbus.h> +#include <intelblocks/tco.h> +#include <soc/romstage.h> + +void pch_init(void) +{ + /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ + tco_configure(); + + /* Program SMBUS_BASE_ADDRESS and Enable it */ + smbus_common_init(); +} diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 2c4ba67e04..7f1be731e8 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -116,6 +116,8 @@ void mainboard_romstage_entry(void) /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); + /* Program PCH init */ + pch_init(); /* initialize Heci interface */ heci_init(HECI1_BASE_ADDRESS); |