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authorKrishna Prasad Bhat <krishna.p.bhat.d@intel.com>2020-12-30 14:01:40 +0530
committerKarthik Ramasubramanian <kramasub@google.com>2021-01-08 01:51:23 +0000
commit830306cc84bc909e7484a9568a7475f89987f857 (patch)
tree42280728a93b763d5b6494ff1b0a3ec7a9483711 /src/soc/intel/icelake/smihandler.c
parent7ae375d3bc77dc74eb76ac6e81313e3fdb010c16 (diff)
downloadcoreboot-830306cc84bc909e7484a9568a7475f89987f857.tar.xz
soc/intel/jasperlake: Enable USB2 PHY SUS PG for s0ix qualification
USBSUSPGQDIS is a disqualifier bit which will allow platform to enter s0ix even if USB2 PHY SUS is not power gated. Disabling this bit will ensure that USB2 PHY SUS is power gated before entering s0ix. BUG=b:175767084 BRANCH=dedede TEST=s0ix works on drawcia and USB wake from s0ix works fine. Change-Id: I20bad3f79141799c88a16272ea822b9e3dede504 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Evan Green <evgreen@chromium.org>
Diffstat (limited to 'src/soc/intel/icelake/smihandler.c')
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