diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2019-09-10 16:00:08 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-09-12 04:28:37 +0000 |
| commit | 0e3c245c6cf4b8fe415c3309098cd51795d90fcf (patch) | |
| tree | bea5daf14bf0114bb12d59e6e1b22e29314a886e /src/soc/intel/icelake | |
| parent | 3eff037f8cbe99f72626c0f25c0989ea638599ef (diff) | |
| download | coreboot-0e3c245c6cf4b8fe415c3309098cd51795d90fcf.tar.xz | |
soc/intel/{cnl, icl}: Cache the TSEG region
This patch helps to save additional ~19ms of booting time in
normal boot and s3 resume on CML-hatch.
BUG=b:140008206
TEST=Verified normal boot time on CML-Hatch with latest coreboot
Without this CL:
Total Time: 929ms
With this CL: (TSEG marked as WB)
Total Time: 910ms
For test marked TSEG as WP/WC:
Total Time: ~920ms
Change-Id: Ie92d2c9e50fa299db1cd8c57a6047ea3adaf1452
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35026
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/icelake')
| -rw-r--r-- | src/soc/intel/icelake/memmap.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index 71368c645a..20c4e6fb7d 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -278,4 +278,7 @@ void fill_postcar_frame(struct postcar_frame *pcf) printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); top_of_ram -= 16*MiB; postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); + + /* Cache the TSEG region */ + postcar_enable_tseg_cache(pcf); } |