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authorNico Huber <nico.h@gmx.de>2018-11-11 02:51:14 +0100
committerNico Huber <nico.h@gmx.de>2019-01-09 22:15:48 +0000
commita96e66a76f21c41b0c15db8d9df1d721f4a8a9af (patch)
tree6cc4301dec4b2ca50a7c0fb43f92c60706bc7e14 /src/soc/intel/icelake
parent3910c4e4882876d70dfef08c6cc3946bc190d9ed (diff)
downloadcoreboot-a96e66a76f21c41b0c15db8d9df1d721f4a8a9af.tar.xz
soc/intel: Clean mess around UART_DEBUG
Everything is wrong here, the Kconfig symbols are only the tip of the iceberg. Based on Kconfig prompts the SoC code performed pad configu- rations! I don't see why the person who configures coreboot should have the board schematics at hand. As a mitigation, we remove the prompts for UART_DEBUG, which is renamed to INTEL_LPSS_UART_FOR_CONSOLE (because the former didn't really say what it's about), and for UART_FOR_CONSOLE in case the former is selec- ted. Change-Id: Ibe2ed3cab0bb04bb23989c22da45299f088c758b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/29573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc/intel/icelake')
-rw-r--r--src/soc/intel/icelake/Kconfig17
-rw-r--r--src/soc/intel/icelake/Makefile.inc12
-rw-r--r--src/soc/intel/icelake/bootblock/bootblock.c2
3 files changed, 7 insertions, 24 deletions
diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig
index 6343ca5d0f..1d687f0224 100644
--- a/src/soc/intel/icelake/Kconfig
+++ b/src/soc/intel/icelake/Kconfig
@@ -62,23 +62,6 @@ config CPU_SPECIFIC_OPTIONS
select UDK_2017_BINDING
select DISPLAY_FSP_VERSION_INFO
-config UART_DEBUG
- bool "Enable UART debug port."
- default n
- select CONSOLE_SERIAL
- select BOOTBLOCK_CONSOLE
- select DRIVERS_UART
- select DRIVERS_UART_8250MEM_32
- select NO_UART_ON_SUPERIO
-
-config UART_FOR_CONSOLE
- int "Index for LPSS UART port to use for console"
- default 2 if DRIVERS_UART_8250MEM_32
- default 0
- help
- Index for LPSS UART port to use for console:
- 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2
-
config DCACHE_RAM_BASE
default 0xfef00000
diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc
index a81edd46a0..74c9182067 100644
--- a/src/soc/intel/icelake/Makefile.inc
+++ b/src/soc/intel/icelake/Makefile.inc
@@ -20,7 +20,7 @@ bootblock-y += memmap.c
bootblock-y += spi.c
bootblock-y += lpc.c
bootblock-y += p2sb.c
-bootblock-$(CONFIG_UART_DEBUG) += uart.c
+bootblock-y += uart.c
romstage-y += gpio.c
romstage-y += gspi.c
@@ -30,7 +30,7 @@ romstage-y += memmap.c
romstage-y += pmutil.c
romstage-y += reset.c
romstage-y += spi.c
-romstage-$(CONFIG_UART_DEBUG) += uart.c
+romstage-y += uart.c
ramstage-y += acpi.c
ramstage-y += chip.c
@@ -52,27 +52,27 @@ ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
ramstage-y += smmrelocate.c
ramstage-y += spi.c
ramstage-y += systemagent.c
-ramstage-$(CONFIG_UART_DEBUG) += uart.c
+ramstage-y += uart.c
ramstage-y += sd.c
smm-y += gpio.c
smm-y += p2sb.c
smm-y += pmutil.c
smm-y += smihandler.c
-smm-$(CONFIG_UART_DEBUG) += uart.c
+smm-y += uart.c
postcar-y += memmap.c
postcar-y += pmutil.c
postcar-y += i2c.c
postcar-y += gspi.c
postcar-y += spi.c
-postcar-$(CONFIG_UART_DEBUG) += uart.c
+postcar-y += uart.c
verstage-y += gspi.c
verstage-y += i2c.c
verstage-y += pmutil.c
verstage-y += spi.c
-verstage-$(CONFIG_UART_DEBUG) += uart.c
+verstage-y += uart.c
CPPFLAGS_common += -I$(src)/soc/intel/icelake
CPPFLAGS_common += -I$(src)/soc/intel/icelake/include
diff --git a/src/soc/intel/icelake/bootblock/bootblock.c b/src/soc/intel/icelake/bootblock/bootblock.c
index 40c2d41b7a..d26fa4210d 100644
--- a/src/soc/intel/icelake/bootblock/bootblock.c
+++ b/src/soc/intel/icelake/bootblock/bootblock.c
@@ -32,7 +32,7 @@ void bootblock_soc_early_init(void)
bootblock_pch_early_init();
bootblock_cpu_init();
pch_early_iorange_init();
- if (IS_ENABLED(CONFIG_UART_DEBUG))
+ if (IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE))
uart_bootblock_init();
}