soc/{amd,intel}/chip: Use local include for chip.h

Change-Id: Ic1fcbf4b54b7d0b5cda04ca9f7fc145050c867b8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

9 files changed, 18 insertions, 9 deletions

diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c
index 1ad89600c1..f16469eb63 100644
--- a/src/soc/intel/icelake/acpi.c
+++ b/src/soc/intel/icelake/acpi.c
@@ -18,7 +18,6 @@
 #include <device/mmio.h>
 #include <arch/smp/mpspec.h>
 #include <cbmem.h>
-#include <chip.h>
 #include <ec/google/chromeec/ec.h>
 #include <intelblocks/cpulib.h>
 #include <intelblocks/pmclib.h>
@@ -32,6 +31,8 @@
 #include <vendorcode/google/chromeos/gnvs.h>
 #include <wrdd.h>
 
+#include "chip.h"
+
 /*
  * List of supported C-states in this processor.
  */
diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c
index 464c25e509..11d14de084 100644
--- a/src/soc/intel/icelake/chip.c
+++ b/src/soc/intel/icelake/chip.c
@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <chip.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <fsp/api.h>
@@ -28,6 +27,8 @@
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
 
+#include "chip.h"
+
 #if CONFIG(HAVE_ACPI_TABLES)
 const char *soc_acpi_name(const struct device *dev)
 {
diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c
index 62bcff6844..b1776a09a4 100644
--- a/src/soc/intel/icelake/cpu.c
+++ b/src/soc/intel/icelake/cpu.c
@@ -16,7 +16,6 @@
 #include <arch/cpu.h>
 #include <console/console.h>
 #include <device/pci.h>
-#include <chip.h>
 #include <cpu/x86/lapic.h>
 #include <cpu/x86/mp.h>
 #include <cpu/x86/msr.h>
@@ -33,6 +32,8 @@
 #include <soc/pm.h>
 #include <soc/smm.h>
 
+#include "chip.h"
+
 static void soc_fsp_load(void)
 {
 	fsps_load(romstage_handoff_is_resume());
diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c
index 3ada73d79c..c1e6dd0d4a 100644
--- a/src/soc/intel/icelake/finalize.c
+++ b/src/soc/intel/icelake/finalize.c
@@ -16,7 +16,6 @@
 #include <arch/io.h>
 #include <device/mmio.h>
 #include <bootstate.h>
-#include <chip.h>
 #include <console/console.h>
 #include <console/post_codes.h>
 #include <cpu/x86/smm.h>
@@ -34,6 +33,8 @@
 #include <soc/systemagent.h>
 #include <stdlib.h>
 
+#include "chip.h"
+
 #define CAMERA1_CLK		0x8000 /* Camera 1 Clock */
 #define CAMERA2_CLK		0x8080 /* Camera 2 Clock */
 #define CAM_CLK_EN		(1 << 1)
diff --git a/src/soc/intel/icelake/include/soc/ramstage.h b/src/soc/intel/icelake/include/soc/ramstage.h
index d0b500d135..d78380a6dc 100644
--- a/src/soc/intel/icelake/include/soc/ramstage.h
+++ b/src/soc/intel/icelake/include/soc/ramstage.h
@@ -16,11 +16,12 @@
 #ifndef _SOC_RAMSTAGE_H_
 #define _SOC_RAMSTAGE_H_
 
-#include <chip.h>
 #include <device/device.h>
 #include <fsp/api.h>
 #include <fsp/util.h>
 
+#include "../../chip.h"
+
 void mainboard_silicon_init_params(FSP_S_CONFIG *params);
 void soc_init_pre_device(void *chip_info);
 
diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c
index 821162e768..7d6e4e6592 100644
--- a/src/soc/intel/icelake/memmap.c
+++ b/src/soc/intel/icelake/memmap.c
@@ -15,7 +15,6 @@
 
 #include <arch/ebda.h>
 #include <cbmem.h>
-#include <chip.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -27,6 +26,8 @@
 #include <soc/systemagent.h>
 #include <stdlib.h>
 
+#include "chip.h"
+
 void smm_region(void **start, size_t *size)
 {
 	*start = (void *)sa_get_tseg_base();
diff --git a/src/soc/intel/icelake/pmc.c b/src/soc/intel/icelake/pmc.c
index ac48da24f8..8f61d70955 100644
--- a/src/soc/intel/icelake/pmc.c
+++ b/src/soc/intel/icelake/pmc.c
@@ -14,7 +14,6 @@
  */
 
 #include <bootstate.h>
-#include <chip.h>
 #include <console/console.h>
 #include <device/mmio.h>
 #include <device/device.h>
@@ -25,6 +24,8 @@
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 
+#include "chip.h"
+
 /*
  * Set which power state system will be after reapplying
  * the power (from G3 State)
diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c
index b0a2b6c0cd..1a0c4ffaee 100644
--- a/src/soc/intel/icelake/romstage/romstage.c
+++ b/src/soc/intel/icelake/romstage/romstage.c
@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <chip.h>
 #include <cpu/x86/mtrr.h>
 #include <cbmem.h>
 #include <console/console.h>
@@ -30,6 +29,8 @@
 #include <string.h>
 #include <timestamp.h>
 
+#include "../chip.h"
+
 #define FSP_SMBIOS_MEMORY_INFO_GUID	\
 {	\
 	0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e,	\
diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c
index ddf642003f..5c00b63720 100644
--- a/src/soc/intel/icelake/smihandler.c
+++ b/src/soc/intel/icelake/smihandler.c
@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <chip.h>
 #include <console/console.h>
 #include <device/pci_def.h>
 #include <intelblocks/fast_spi.h>
@@ -25,6 +24,8 @@
 #include <soc/pcr_ids.h>
 #include <soc/pm.h>
 
+#include "chip.h"
+
 #define CSME0_FBE	0xf
 #define CSME0_BAR	0x0
 #define CSME0_FID	0xb0