summaryrefslogtreecommitdiff
path: root/src/soc/intel/icelake
diff options
context:
space:
mode:
authorMichael Niewöhner <foss@mniewoehner.de>2019-10-22 23:05:06 +0200
committerNico Huber <nico.h@gmx.de>2019-11-04 19:25:02 +0000
commit7736bfc443a913a9cde46406bcfc38015ec71f47 (patch)
tree5b107551301bbaadc538b0c2ac7c52125462beb3 /src/soc/intel/icelake
parente75a64f822931a5fbdd80f20c4d168a5c346e01a (diff)
downloadcoreboot-7736bfc443a913a9cde46406bcfc38015ec71f47.tar.xz
soc/intel/sgx: convert SGX and PRMRR devicetree options to Kconfig
The devicetree is not made for user-choosable options, thus introduce Kconfig options for both SGX and the corresponding PRMRR size. The PRMRR size Kconfig has been implemented as a maximum value. At runtime the final PRMRR size gets selected by checking the supported values in MSR_PRMRR_VALID_CONFIG and trying to select the value nearest to the chosen one. When "Maximum" is chosen, the highest possibly value from the MSR gets used. When a too strict limit is set, coreboot will die, printing an error message. Tested successfully on X11SSM-F Change-Id: I5f08e85898304bba6680075ca5d6bce26aef9a4d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/icelake')
-rw-r--r--src/soc/intel/icelake/chip.h8
-rw-r--r--src/soc/intel/icelake/romstage/fsp_params.c3
2 files changed, 4 insertions, 7 deletions
diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h
index fc9341c58b..ec625a0049 100644
--- a/src/soc/intel/icelake/chip.h
+++ b/src/soc/intel/icelake/chip.h
@@ -206,13 +206,9 @@ struct soc_intel_icelake_config {
/* Enable C6 DRAM */
uint8_t enable_c6dram;
- /*
- * PRMRR size setting with below options
- * 0x00100000 - 1MiB
- * 0x02000000 - 32MiB and beyond
- */
- uint32_t PrmrrSize;
+
uint8_t PmTimerDisabled;
+
/* Desired platform debug type. */
enum {
DebugConsent_Disabled,
diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c
index 5bf34213f0..1f9960410e 100644
--- a/src/soc/intel/icelake/romstage/fsp_params.c
+++ b/src/soc/intel/icelake/romstage/fsp_params.c
@@ -16,6 +16,7 @@
#include <assert.h>
#include <console/console.h>
#include <fsp/util.h>
+#include <intelblocks/cpulib.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <soc/romstage.h>
@@ -60,7 +61,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
mask |= (1 << i);
}
m_cfg->PcieRpEnableMask = mask;
- m_cfg->PrmrrSize = config->PrmrrSize;
+ m_cfg->PrmrrSize = get_prmrr_size();
m_cfg->EnableC6Dram = config->enable_c6dram;
/* Disable BIOS Guard */
m_cfg->BiosGuard = 0;