summaryrefslogtreecommitdiff
path: root/src/soc/intel/icelake
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-17 20:51:08 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-26 21:08:41 +0000
commitcd7a70f4879ff6e0f3e334ddf1031ccf0c0d31cf (patch)
treeb0438431df0943ab5f0fa9d80a99fc265130ac23 /src/soc/intel/icelake
parent16248e89ecf73a76e5d9e9e2de46146f7ffece88 (diff)
downloadcoreboot-cd7a70f4879ff6e0f3e334ddf1031ccf0c0d31cf.tar.xz
soc/intel: Use common romstage code
This provides stack guards with checking and common entry into postcar. The code in cpu/intel/car/romstage.c is candidate for becoming architectural so function prototype is moved to <arch/romstage.h>. Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/icelake')
-rw-r--r--src/soc/intel/icelake/romstage/romstage.c20
1 files changed, 6 insertions, 14 deletions
diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c
index 8312f178e4..67ef2bb6ce 100644
--- a/src/soc/intel/icelake/romstage/romstage.c
+++ b/src/soc/intel/icelake/romstage/romstage.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-#include <arch/cpu.h>
#include <arch/romstage.h>
#include <cpu/x86/mtrr.h>
#include <cbmem.h>
@@ -112,15 +111,11 @@ static void save_dimm_info(void)
printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
}
-asmlinkage void car_stage_entry(void)
+void mainboard_romstage_entry(void)
{
bool s3wake;
- struct postcar_frame pcf;
- uintptr_t top_of_ram;
struct chipset_power_state *ps = pmc_get_power_state();
- console_init();
-
/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
systemagent_early_init();
/* initialize Heci interface */
@@ -132,9 +127,11 @@ asmlinkage void car_stage_entry(void)
pmc_set_disb();
if (!s3wake)
save_dimm_info();
- if (postcar_frame_init(&pcf, 0))
- die("Unable to initialize postcar frame.\n");
+}
+void fill_postcar_frame(struct postcar_frame *pcf)
+{
+ uintptr_t top_of_ram;
/*
* We need to make sure ramstage will be run cached. At this
* point exact location of ramstage in cbmem is not known.
@@ -144,10 +141,5 @@ asmlinkage void car_stage_entry(void)
top_of_ram = (uintptr_t) cbmem_top();
printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
top_of_ram -= 16*MiB;
- postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
-
- /* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
-
- run_postcar_phase(&pcf);
+ postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
}