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authorPaul Menzel <pmenzel@molgen.mpg.de>2020-03-11 20:14:15 +0100
committerPatrick Georgi <pgeorgi@google.com>2020-03-15 12:57:02 +0000
commitdd57ac2f35954af84e4a20451284bbdeaf7f4aa8 (patch)
tree4feb80ee0bce3468912b721355366a8f6ab4fe16 /src/soc/intel/icelake
parent9f111859207faf24406dab335eb1192960e200f9 (diff)
downloadcoreboot-dd57ac2f35954af84e4a20451284bbdeaf7f4aa8.tar.xz
soc/intel/icelake: Re-flow comment for 96 characters
Change-Id: I7a5d7bb476c33ab995136eb47ef0258b483a42ef Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/icelake')
-rw-r--r--src/soc/intel/icelake/romstage/fsp_params.c5
1 files changed, 1 insertions, 4 deletions
diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c
index 99f606b4e2..5aea2ee8af 100644
--- a/src/soc/intel/icelake/romstage/fsp_params.c
+++ b/src/soc/intel/icelake/romstage/fsp_params.c
@@ -30,10 +30,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
uint32_t mask = 0;
if (!dev || !dev->enabled) {
- /*
- * Skip IGD initialization in FSP if device
- * is disabled in devicetree.cb.
- */
+ /* Skip IGD initialization in FSP if device is disabled in devicetree.cb. */
m_cfg->InternalGfx = 0;
m_cfg->IgdDvmt50PreAlloc = 0;
} else {