soc/intel/jasperlake: Remove Tiger Lake SoC code from Jasper Lake

This is a follow-up patch to initial copy patch for Jasper Lake SoC.
Remove all Tiger Lake specfic code from Jasper Lake SoC code.

BUG=b:150217037

Change-Id: I44dc6bf55ca18a3f0c350f5c3e9fae2996958648
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39824
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

7 files changed, 175 insertions, 443 deletions

diff --git a/src/soc/intel/jasperlake/acpi/pci_irqs.asl b/src/soc/intel/jasperlake/acpi/pci_irqs.asl
index 474a6d6c1e..086282e733 100644
--- a/src/soc/intel/jasperlake/acpi/pci_irqs.asl
+++ b/src/soc/intel/jasperlake/acpi/pci_irqs.asl
@@ -13,8 +13,129 @@
  * GNU General Public License for more details.
  */
 
-#if CONFIG(SOC_INTEL_TIGERLAKE_COPY)
-	#include "pci_irqs_tgl.asl"
-#else
-	#include "pci_irqs_jsl.asl"
-#endif
+#include <soc/irq.h>
+
+Name (PICP, Package () {
+	/* cAVS, SMBus, GbE, Northpeak */
+	Package(){0x001FFFFF, 3, 0, cAVS_INTA_IRQ },
+	Package(){0x001FFFFF, 4, 0, SMBUS_INTB_IRQ },
+	Package(){0x001FFFFF, 6, 0, GbE_INTC_IRQ },
+	Package(){0x001FFFFF, 7, 0, TRACE_HUB_INTD_IRQ },
+	/* SerialIo */
+	Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ },
+	Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ },
+	Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ },
+	Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ },
+	/* PCI Express Port 1-8 */
+	Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ },
+	Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ },
+	Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ },
+	Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ },
+	Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ },
+	Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ },
+	Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ },
+	Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ },
+	/* eMMC */
+	Package(){0x001AFFFF, 0, 0, eMMC_IRQ },
+	/* SerialIo */
+	Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ },
+	Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ },
+	Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ },
+	/* SATA controller */
+	Package(){0x0017FFFF, 0, 0, SATA_IRQ },
+	/* CSME (HECI, IDE-R, Keyboard and Text redirection */
+	Package(){0x0016FFFF, 0, 0, HECI_1_IRQ },
+	Package(){0x0016FFFF, 1, 0, HECI_2_IRQ },
+	Package(){0x0016FFFF, 2, 0, IDER_IRQ },
+	Package(){0x0016FFFF, 3, 0, KT_IRQ },
+	Package(){0x0016FFFF, 4, 0, HECI_3_IRQ },
+	Package(){0x0016FFFF, 5, 0, HECI_4_IRQ },
+	/* SerialIo */
+	Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ },
+	Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },
+	Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ },
+	Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ },
+	/* D20: xHCI, OTG, SRAM, CNVi WiFi, SD */
+	Package(){0x0014FFFF, 0, 0, XHCI_IRQ },
+	Package(){0x0014FFFF, 1, 0, OTG_IRQ },
+	Package(){0x0014FFFF, 2, 0, PMC_SRAM_IRQ },
+	Package(){0x0014FFFF, 3, 0, CNViWIFI_IRQ },
+	Package(){0x0014FFFF, 5, 0, SD_IRQ },
+	/* SerialIo */
+	Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ },
+	/* SA IGFX Device */
+	Package(){0x0002FFFF, 0, 0, IGFX_IRQ },
+	/* SA Thermal Device */
+	Package(){0x0004FFFF, 0, 0, SA_THERMAL_IRQ },
+	/* SA IPU Device */
+	Package(){0x0005FFFF, 0, 0, IPU_IRQ },
+	/* SA GNA Device */
+	Package(){0x0008FFFF, 0, 0, GNA_IRQ },
+})
+
+Name (PICN, Package () {
+	/* D31: cAVS, SMBus, GbE, Northpeak */
+	Package () { 0x001FFFFF, 3, 0, 11 },
+	Package () { 0x001FFFFF, 4, 0, 10 },
+	Package () { 0x001FFFFF, 6, 0, 11 },
+	Package () { 0x001FFFFF, 7, 0, 11 },
+	/* D30: SerialIo */
+	Package () {0x001EFFFF, 0, 0, 11 },
+	Package () {0x001EFFFF, 1, 0, 10 },
+	Package () {0x001EFFFF, 2, 0, 11 },
+	Package () {0x001EFFFF, 3, 0, 11 },
+	/* D28: PCI Express Port 1-8 */
+	Package () { 0x001CFFFF, 0, 0, 11 },
+	Package () { 0x001CFFFF, 1, 0, 10 },
+	Package () { 0x001CFFFF, 2, 0, 11 },
+	Package () { 0x001CFFFF, 3, 0, 11 },
+	Package () { 0x001CFFFF, 4, 0, 11 },
+	Package () { 0x001CFFFF, 5, 0, 10 },
+	Package () { 0x001CFFFF, 6, 0, 11 },
+	Package () { 0x001CFFFF, 7, 0, 11 },
+	/* D26: eMMC */
+	Package(){0x001AFFFF, 0, 0, 11 },
+	/* D25: SerialIo */
+	Package () {0x0019FFFF, 0, 0, 11 },
+	Package () {0x0019FFFF, 1, 0, 10 },
+	Package () {0x0019FFFF, 2, 0, 11 },
+	/* D23: SATA controller */
+	Package () { 0x0017FFFF, 0, 0, 11 },
+	/* D22: CSME (HECI, IDE-R, KT redirection */
+	Package () { 0x0016FFFF, 0, 0, 11 },
+	Package () { 0x0016FFFF, 1, 0, 10 },
+	Package () { 0x0016FFFF, 2, 0, 11 },
+	Package () { 0x0016FFFF, 3, 0, 11 },
+	Package () { 0x0016FFFF, 4, 0, 11 },
+	Package () { 0x0016FFFF, 5, 0, 11 },
+	/* D21: SerialIo */
+	Package () {0x0015FFFF, 0, 0, 11 },
+	Package () {0x0015FFFF, 1, 0, 10 },
+	Package () {0x0015FFFF, 2, 0, 11 },
+	Package () {0x0015FFFF, 3, 0, 11 },
+	/* D20: xHCI, OTG, SRAM, CNVi WiFi, SD */
+	Package () { 0x0014FFFF, 0, 0, 11 },
+	Package () { 0x0014FFFF, 1, 0, 10 },
+	Package () { 0x0014FFFF, 2, 0, 11 },
+	Package () { 0x0014FFFF, 3, 0, 11 },
+	Package () { 0x0014FFFF, 5, 0, 11 },
+	/* D18: SerialIo */
+	Package () {0x0012FFFF, 6, 0, 11 },
+	/* SA IGFX Device */
+	Package () {0x0002FFFF, 0, 0, 11 },
+	/* SA Thermal Device */
+	Package () { 0x0004FFFF, 0, 0, 11 },
+	/* SA IPU Device */
+	Package () { 0x0005FFFF, 0, 0, 11 },
+	/* SA GNA Device */
+	Package () { 0x0008FFFF, 0, 0, 11 },
+})
+
+Method (_PRT)
+{
+	If (PICM) {
+		Return (^PICP)
+	} Else {
+		Return (^PICN)
+	}
+}
diff --git a/src/soc/intel/jasperlake/acpi/pci_irqs_jsl.asl b/src/soc/intel/jasperlake/acpi/pci_irqs_jsl.asl
deleted file mode 100644
index 086282e733..0000000000
--- a/src/soc/intel/jasperlake/acpi/pci_irqs_jsl.asl
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <soc/irq.h>
-
-Name (PICP, Package () {
-	/* cAVS, SMBus, GbE, Northpeak */
-	Package(){0x001FFFFF, 3, 0, cAVS_INTA_IRQ },
-	Package(){0x001FFFFF, 4, 0, SMBUS_INTB_IRQ },
-	Package(){0x001FFFFF, 6, 0, GbE_INTC_IRQ },
-	Package(){0x001FFFFF, 7, 0, TRACE_HUB_INTD_IRQ },
-	/* SerialIo */
-	Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ },
-	Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ },
-	Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ },
-	Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ },
-	/* PCI Express Port 1-8 */
-	Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ },
-	Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ },
-	Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ },
-	Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ },
-	Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ },
-	Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ },
-	Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ },
-	Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ },
-	/* eMMC */
-	Package(){0x001AFFFF, 0, 0, eMMC_IRQ },
-	/* SerialIo */
-	Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ },
-	Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ },
-	Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ },
-	/* SATA controller */
-	Package(){0x0017FFFF, 0, 0, SATA_IRQ },
-	/* CSME (HECI, IDE-R, Keyboard and Text redirection */
-	Package(){0x0016FFFF, 0, 0, HECI_1_IRQ },
-	Package(){0x0016FFFF, 1, 0, HECI_2_IRQ },
-	Package(){0x0016FFFF, 2, 0, IDER_IRQ },
-	Package(){0x0016FFFF, 3, 0, KT_IRQ },
-	Package(){0x0016FFFF, 4, 0, HECI_3_IRQ },
-	Package(){0x0016FFFF, 5, 0, HECI_4_IRQ },
-	/* SerialIo */
-	Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ },
-	Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },
-	Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ },
-	Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ },
-	/* D20: xHCI, OTG, SRAM, CNVi WiFi, SD */
-	Package(){0x0014FFFF, 0, 0, XHCI_IRQ },
-	Package(){0x0014FFFF, 1, 0, OTG_IRQ },
-	Package(){0x0014FFFF, 2, 0, PMC_SRAM_IRQ },
-	Package(){0x0014FFFF, 3, 0, CNViWIFI_IRQ },
-	Package(){0x0014FFFF, 5, 0, SD_IRQ },
-	/* SerialIo */
-	Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ },
-	/* SA IGFX Device */
-	Package(){0x0002FFFF, 0, 0, IGFX_IRQ },
-	/* SA Thermal Device */
-	Package(){0x0004FFFF, 0, 0, SA_THERMAL_IRQ },
-	/* SA IPU Device */
-	Package(){0x0005FFFF, 0, 0, IPU_IRQ },
-	/* SA GNA Device */
-	Package(){0x0008FFFF, 0, 0, GNA_IRQ },
-})
-
-Name (PICN, Package () {
-	/* D31: cAVS, SMBus, GbE, Northpeak */
-	Package () { 0x001FFFFF, 3, 0, 11 },
-	Package () { 0x001FFFFF, 4, 0, 10 },
-	Package () { 0x001FFFFF, 6, 0, 11 },
-	Package () { 0x001FFFFF, 7, 0, 11 },
-	/* D30: SerialIo */
-	Package () {0x001EFFFF, 0, 0, 11 },
-	Package () {0x001EFFFF, 1, 0, 10 },
-	Package () {0x001EFFFF, 2, 0, 11 },
-	Package () {0x001EFFFF, 3, 0, 11 },
-	/* D28: PCI Express Port 1-8 */
-	Package () { 0x001CFFFF, 0, 0, 11 },
-	Package () { 0x001CFFFF, 1, 0, 10 },
-	Package () { 0x001CFFFF, 2, 0, 11 },
-	Package () { 0x001CFFFF, 3, 0, 11 },
-	Package () { 0x001CFFFF, 4, 0, 11 },
-	Package () { 0x001CFFFF, 5, 0, 10 },
-	Package () { 0x001CFFFF, 6, 0, 11 },
-	Package () { 0x001CFFFF, 7, 0, 11 },
-	/* D26: eMMC */
-	Package(){0x001AFFFF, 0, 0, 11 },
-	/* D25: SerialIo */
-	Package () {0x0019FFFF, 0, 0, 11 },
-	Package () {0x0019FFFF, 1, 0, 10 },
-	Package () {0x0019FFFF, 2, 0, 11 },
-	/* D23: SATA controller */
-	Package () { 0x0017FFFF, 0, 0, 11 },
-	/* D22: CSME (HECI, IDE-R, KT redirection */
-	Package () { 0x0016FFFF, 0, 0, 11 },
-	Package () { 0x0016FFFF, 1, 0, 10 },
-	Package () { 0x0016FFFF, 2, 0, 11 },
-	Package () { 0x0016FFFF, 3, 0, 11 },
-	Package () { 0x0016FFFF, 4, 0, 11 },
-	Package () { 0x0016FFFF, 5, 0, 11 },
-	/* D21: SerialIo */
-	Package () {0x0015FFFF, 0, 0, 11 },
-	Package () {0x0015FFFF, 1, 0, 10 },
-	Package () {0x0015FFFF, 2, 0, 11 },
-	Package () {0x0015FFFF, 3, 0, 11 },
-	/* D20: xHCI, OTG, SRAM, CNVi WiFi, SD */
-	Package () { 0x0014FFFF, 0, 0, 11 },
-	Package () { 0x0014FFFF, 1, 0, 10 },
-	Package () { 0x0014FFFF, 2, 0, 11 },
-	Package () { 0x0014FFFF, 3, 0, 11 },
-	Package () { 0x0014FFFF, 5, 0, 11 },
-	/* D18: SerialIo */
-	Package () {0x0012FFFF, 6, 0, 11 },
-	/* SA IGFX Device */
-	Package () {0x0002FFFF, 0, 0, 11 },
-	/* SA Thermal Device */
-	Package () { 0x0004FFFF, 0, 0, 11 },
-	/* SA IPU Device */
-	Package () { 0x0005FFFF, 0, 0, 11 },
-	/* SA GNA Device */
-	Package () { 0x0008FFFF, 0, 0, 11 },
-})
-
-Method (_PRT)
-{
-	If (PICM) {
-		Return (^PICP)
-	} Else {
-		Return (^PICN)
-	}
-}
diff --git a/src/soc/intel/jasperlake/acpi/pci_irqs_tgl.asl b/src/soc/intel/jasperlake/acpi/pci_irqs_tgl.asl
deleted file mode 100644
index 7f632ba32e..0000000000
--- a/src/soc/intel/jasperlake/acpi/pci_irqs_tgl.asl
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <soc/irq.h>
-
-Name (PICP, Package () {
-	/* D31:HSA, SMBUS, TraceHUB */
-	Package(){0x001FFFFF, 3, 0, HDA_IRQ },
-	Package(){0x001FFFFF, 4, 0, SMBUS_IRQ },
-	Package(){0x001FFFFF, 7, 0, TRACEHUB_IRQ },
-	/* D30: UART0, UART1, SPI0, SPI1 */
-	Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ },
-	Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ },
-	Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ },
-	Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ },
-	/* D29: RP9 ~ RP12 */
-	Package(){0x001DFFFF, 0, 0, PCIE_9_IRQ },
-	Package(){0x001DFFFF, 1, 0, PCIE_10_IRQ },
-	Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ },
-	Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ },
-	/* D28: RP1 ~ RP8 */
-	Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ },
-	Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ },
-	Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ },
-	Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ },
-	Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ },
-	Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ },
-	Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ },
-	Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ },
-	/* D25: I2C4, I2C5, UART2 */
-	Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ },
-	Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ },
-	Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ },
-	/* D23: SATA */
-	Package(){0x0017FFFF, 0, 0, SATA_IRQ },
-	/* D22: CSME */
-	Package(){0x0016FFFF, 0, 0, HECI_1_IRQ },
-	Package(){0x0016FFFF, 1, 0, HECI_2_IRQ },
-	Package(){0x0016FFFF, 4, 0, HECI_3_IRQ },
-	Package(){0x0016FFFF, 5, 0, HECI_4_IRQ },
-	/* D21: I2C0 ~ I2C3 */
-	Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ },
-	Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },
-	Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ },
-	Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ },
-	/* D20: xHCI, xDCI, SRAM, CNVI_WIFI */
-	Package(){0x0014FFFF, 0, 0, xHCI_IRQ },
-	Package(){0x0014FFFF, 1, 0, xDCI_IRQ },
-	Package(){0x0014FFFF, 3, 0, CNVI_WIFI_IRQ },
-	/* D19: SPI3 */
-	Package(){0x0013FFFF, 0, 0, LPSS_SPI3_IRQ },
-	/* D18: ISH, SPI2 */
-	Package(){0x0012FFFF, 0, 0, ISH_IRQ },
-	Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ },
-	/* D16: CNVI_BT, TCH0, TCH1 */
-	Package(){0x0010FFFF, 2, 0, CNVI_BT_IRQ },
-	Package(){0x0010FFFF, 6, 0, THC0_IRQ },
-	Package(){0x0010FFFF, 7, 0, THC1_IRQ },
-	/* D13: xHCI, xDCI */
-	Package(){0x000DFFFF, 0, 0, xHCI_IRQ },
-	Package(){0x000DFFFF, 1, 0, xDCI_IRQ },
-	/* D8: GNA */
-	Package(){0x0008FFFF, 0, 0, GNA_IRQ },
-	/* D7: TBT PCIe */
-	Package(){0x0007FFFF, 0, 0, TBT_PCIe0_IRQ },
-	Package(){0x0007FFFF, 1, 0, TBT_PCIe1_IRQ },
-	Package(){0x0007FFFF, 2, 0, TBT_PCIe2_IRQ },
-	Package(){0x0007FFFF, 3, 0, TBT_PCIe3_IRQ },
-	/* D6: PEG60 */
-	Package(){0x0006FFFF, 0, 0, PEG_IRQ },
-	/* D5: IPU Device */
-	Package(){0x0005FFFF, 0, 0, IPU_IRQ },
-	/* D4:  Thermal Device */
-	Package(){0x0004FFFF, 0, 0, THERMAL_IRQ },
-	/* D2: IGFX */
-	Package(){0x0002FFFF, 0, 0, IGFX_IRQ },
-})
-
-Name (PICN, Package () {
-	/* D31:HSA, SMBUS, TraceHUB*/
-	Package () { 0x001FFFFF, 3, 0, 11 },
-	Package () { 0x001FFFFF, 4, 0, 11 },
-	Package () { 0x001FFFFF, 7, 0, 11 },
-	/* D30: UART0, UART1, SPI0, SPI1 */
-	Package () { 0x001EFFFF, 0, 0, 11 },
-	Package () { 0x001EFFFF, 1, 0, 10 },
-	Package () { 0x001EFFFF, 2, 0, 11 },
-	Package () { 0x001EFFFF, 3, 0, 11 },
-	/* D29: RP9 ~ RP12 */
-	Package () { 0x001DFFFF, 0, 0, 11 },
-	Package () { 0x001DFFFF, 1, 0, 10 },
-	Package () { 0x001DFFFF, 2, 0, 11 },
-	Package () { 0x001DFFFF, 3, 0, 11 },
-	/* D28: RP1 ~ RP8 */
-	Package () { 0x001CFFFF, 0, 0, 11 },
-	Package () { 0x001CFFFF, 1, 0, 10 },
-	Package () { 0x001CFFFF, 2, 0, 11 },
-	Package () { 0x001CFFFF, 3, 0, 11 },
-	Package () { 0x001CFFFF, 4, 0, 11 },
-	Package () { 0x001CFFFF, 5, 0, 10 },
-	Package () { 0x001CFFFF, 6, 0, 11 },
-	Package () { 0x001CFFFF, 7, 0, 11 },
-	/* D25: I2C4, I2C5, UART2 */
-	Package(){0x0019FFFF, 0, 0, 11 },
-	Package(){0x0019FFFF, 1, 0, 10 },
-	Package(){0x0019FFFF, 2, 0, 11 },
-	/* D23: SATA */
-	Package () { 0x0017FFFF, 0, 0, 11 },
-	/* D22: CSME */
-	Package(){0x0016FFFF, 0, 0, 11 },
-	Package(){0x0016FFFF, 1, 0, 10 },
-	Package(){0x0016FFFF, 4, 0, 11 },
-	Package(){0x0016FFFF, 5, 0, 11 },
-	/* D21: I2C0 ~ I2C3 */
-	Package(){0x0015FFFF, 0, 0, 11 },
-	Package(){0x0015FFFF, 1, 0, 10 },
-	Package(){0x0015FFFF, 2, 0, 11 },
-	Package(){0x0015FFFF, 3, 0, 11 },
-	/* D19: SPI3 */
-	Package(){0x0013FFFF, 0, 0, 11 },
-	/* D18: ISH, SPI2 */
-	Package(){0x0012FFFF, 0, 0, 11 },
-	Package(){0x0012FFFF, 6, 0, 11 },,
-	/* D16: CNVI_BT, TCH0, TCH1 */
-	Package(){0x0010FFFF, 2, 0, 11 },
-	Package(){0x0010FFFF, 6, 0, 11 },
-	Package(){0x0010FFFF, 7, 0, 10 },
-	/* D13: xHCI, xDCI */
-	Package(){0x000DFFFF, 0, 0, 11 },
-	Package(){0x000DFFFF, 1, 0, 10 },
-	/* D8: GNA */
-	Package(){0x0008FFFF, 0, 0, 11 },
-	/* D7: TBT PCIe */
-	Package(){0x0007FFFF, 0, 0, 11 },
-	Package(){0x0007FFFF, 1, 0, 10 },
-	Package(){0x0007FFFF, 2, 0, 11 },
-	Package(){0x0007FFFF, 3, 0, 11 },
-	/* D6: PEG60 */
-	Package(){0x0006FFFF, 0, 0, 11 },
-	/* D5: IPU Device */
-	Package(){0x0005FFFF, 0, 0, 11 },
-	/* D4:  Thermal Device */
-	Package(){0x0004FFFF, 0, 0, 11 },
-	/* D2: IGFX */
-	Package(){0x0002FFFF, 0, 0, 11 },
-})
-
-Method (_PRT)
-{
-	If (PICM) {
-		Return (^PICP)
-	} Else {
-		Return (^PICN)
-	}
-}
diff --git a/src/soc/intel/jasperlake/acpi/pmc.asl b/src/soc/intel/jasperlake/acpi/pmc.asl
index 6dd2d35354..0e3e24d94e 100644
--- a/src/soc/intel/jasperlake/acpi/pmc.asl
+++ b/src/soc/intel/jasperlake/acpi/pmc.asl
@@ -19,7 +19,7 @@ Scope (\_SB.PCI0) {
 	Device (PMC)
 	{
 		Name (_HID, "INTC1026")
-		Name (_DDN, "Intel(R) Tiger Lake IPC Controller")
+		Name (_DDN, "Intel(R) Jasper Lake IPC Controller")
 		/*
 		 * PCH preserved 32 MB MMIO range from 0xFC800000 to 0xFE7FFFFF.
 		 * 64KB (0xFE000000 - 0xFE00FFFF) for PMC MBAR.
diff --git a/src/soc/intel/jasperlake/acpi/xhci.asl b/src/soc/intel/jasperlake/acpi/xhci.asl
index 9baf67ac5a..41be89ace1 100644
--- a/src/soc/intel/jasperlake/acpi/xhci.asl
+++ b/src/soc/intel/jasperlake/acpi/xhci.asl
@@ -12,8 +12,51 @@
  * GNU General Public License for more details.
  */
 
-#if CONFIG(SOC_INTEL_TIGERLAKE_COPY)
-	#include "xhci_tgl.asl"
-#else
-	#include "xhci_jsl.asl"
-#endif
+#include <soc/gpe.h>
+
+/* XHCI Controller 0:14.0 */
+
+Device (XHCI)
+{
+	Name (_ADR, 0x00140000)
+
+	Name (_PRW, Package () { GPE0_PME_B0, 3 })
+
+	Name (_S3D, 3)	/* D3 supported in S3 */
+	Name (_S0W, 3)	/* D3 can wake device in S0 */
+	Name (_S3W, 3)	/* D3 can wake system from S3 */
+
+	Method (_PS0, 0, Serialized)
+	{
+
+	}
+
+	Method (_PS3, 0, Serialized)
+	{
+
+	}
+
+	/* Root Hub for Jasperlake PCH */
+	Device (RHUB)
+	{
+		Name (_ADR, Zero)
+
+		/* USB2 */
+		Device (HS01) { Name (_ADR, 1) }
+		Device (HS02) { Name (_ADR, 2) }
+		Device (HS03) { Name (_ADR, 3) }
+		Device (HS04) { Name (_ADR, 4) }
+		Device (HS05) { Name (_ADR, 5) }
+		Device (HS06) { Name (_ADR, 6) }
+		Device (HS07) { Name (_ADR, 7) }
+		Device (HS08) { Name (_ADR, 8) }
+
+		/* USB3 */
+		Device (SS01) { Name (_ADR, 9) }
+		Device (SS02) { Name (_ADR, 10) }
+		Device (SS03) { Name (_ADR, 11) }
+		Device (SS04) { Name (_ADR, 12) }
+		Device (SS05) { Name (_ADR, 13) }
+		Device (SS06) { Name (_ADR, 14) }
+	}
+}
diff --git a/src/soc/intel/jasperlake/acpi/xhci_jsl.asl b/src/soc/intel/jasperlake/acpi/xhci_jsl.asl
deleted file mode 100644
index 41be89ace1..0000000000
--- a/src/soc/intel/jasperlake/acpi/xhci_jsl.asl
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <soc/gpe.h>
-
-/* XHCI Controller 0:14.0 */
-
-Device (XHCI)
-{
-	Name (_ADR, 0x00140000)
-
-	Name (_PRW, Package () { GPE0_PME_B0, 3 })
-
-	Name (_S3D, 3)	/* D3 supported in S3 */
-	Name (_S0W, 3)	/* D3 can wake device in S0 */
-	Name (_S3W, 3)	/* D3 can wake system from S3 */
-
-	Method (_PS0, 0, Serialized)
-	{
-
-	}
-
-	Method (_PS3, 0, Serialized)
-	{
-
-	}
-
-	/* Root Hub for Jasperlake PCH */
-	Device (RHUB)
-	{
-		Name (_ADR, Zero)
-
-		/* USB2 */
-		Device (HS01) { Name (_ADR, 1) }
-		Device (HS02) { Name (_ADR, 2) }
-		Device (HS03) { Name (_ADR, 3) }
-		Device (HS04) { Name (_ADR, 4) }
-		Device (HS05) { Name (_ADR, 5) }
-		Device (HS06) { Name (_ADR, 6) }
-		Device (HS07) { Name (_ADR, 7) }
-		Device (HS08) { Name (_ADR, 8) }
-
-		/* USB3 */
-		Device (SS01) { Name (_ADR, 9) }
-		Device (SS02) { Name (_ADR, 10) }
-		Device (SS03) { Name (_ADR, 11) }
-		Device (SS04) { Name (_ADR, 12) }
-		Device (SS05) { Name (_ADR, 13) }
-		Device (SS06) { Name (_ADR, 14) }
-	}
-}
diff --git a/src/soc/intel/jasperlake/acpi/xhci_tgl.asl b/src/soc/intel/jasperlake/acpi/xhci_tgl.asl
deleted file mode 100644
index b97f52052b..0000000000
--- a/src/soc/intel/jasperlake/acpi/xhci_tgl.asl
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <soc/gpe.h>
-
-/* XHCI Controller 0:14.0 */
-
-Device (XHCI)
-{
-	Name (_ADR, 0x00140000)
-
-	Name (_PRW, Package () { GPE0_PME_B0, 3 })
-
-	Name (_S3D, 3)	/* D3 supported in S3 */
-	Name (_S0W, 3)	/* D3 can wake device in S0 */
-	Name (_S3W, 3)	/* D3 can wake system from S3 */
-
-	Method (_PS0, 0, Serialized)
-	{
-
-	}
-
-	Method (_PS3, 0, Serialized)
-	{
-
-	}
-
-	/* Root Hub for Tigerlake-LP PCH */
-	Device (RHUB)
-	{
-		Name (_ADR, Zero)
-
-		/* USB2 */
-		Device (HS01) { Name (_ADR, 1) }
-		Device (HS02) { Name (_ADR, 2) }
-		Device (HS03) { Name (_ADR, 3) }
-		Device (HS04) { Name (_ADR, 4) }
-		Device (HS05) { Name (_ADR, 5) }
-		Device (HS06) { Name (_ADR, 6) }
-		Device (HS07) { Name (_ADR, 7) }
-		Device (HS08) { Name (_ADR, 8) }
-		Device (HS09) { Name (_ADR, 9) }
-		Device (HS10) { Name (_ADR, 10) }
-
-		/* USB3 */
-		Device (SS01) { Name (_ADR, 13) }
-		Device (SS02) { Name (_ADR, 14) }
-		Device (SS03) { Name (_ADR, 15) }
-		Device (SS04) { Name (_ADR, 16) }
-	}
-}