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| author | Ronak Kanabar <ronak.kanabar@intel.com> | 2020-05-04 17:54:48 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-12 20:06:37 +0000 |
| commit | 7f9bca73286c393a919112133d50a767500cfa95 (patch) | |
| tree | 334bc69b2cbccaea07a21a710a4ff82516feb38d /src/soc/intel/jasperlake/chip.h | |
| parent | 727fe925649cadc2803e56b8d5ddb070ddc36a43 (diff) | |
| download | coreboot-7f9bca73286c393a919112133d50a767500cfa95.tar.xz | |
soc/intel/jasperlake: Add SATA related UPDs configuration
This patch control SATA related UPDs based on the devicetree
configuration as per each board's requirement.
BUG=b:155595624
BRANCH=None
TEST=Build, boot JSLRVP, Verified UPD values from FSP log
Change-Id: I4f7e7508b8cd483508293ee3e7b760574d8f025f
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Diffstat (limited to 'src/soc/intel/jasperlake/chip.h')
| -rw-r--r-- | src/soc/intel/jasperlake/chip.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 548d0ee2d1..7a6a7fd0dd 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -83,7 +83,6 @@ struct soc_intel_jasperlake_config { uint16_t usb3_wake_enable_bitmap; /* SATA related */ - uint8_t SataEnable; uint8_t SataMode; uint8_t SataSalpSupport; uint8_t SataPortsEnable[8]; |