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| author | Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> | 2020-06-18 18:53:23 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-30 19:09:43 +0000 |
| commit | f4a940c23613b988512f46acf45b4e0eb338e2c5 (patch) | |
| tree | 791abc342048fa0bf9abbdb239749df6e9e9d300 /src/soc/intel/jasperlake/cpu.c | |
| parent | 9f9b97e6bc57a9a80c6f75046a3987b223433e10 (diff) | |
| download | coreboot-f4a940c23613b988512f46acf45b4e0eb338e2c5.tar.xz | |
jasperlake: enable tcc_offset functionality
This enables Thermal Control Circuit (TCC) activation feature to set
tcc_offset value to new value in devicetree.
BUG=None
BRANCH=None
TEST=Built for dedede platform and verified the MSR value
Change-Id: I58e4fa362f20efeef84e06e64d70ee7c4f9554d6
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/jasperlake/cpu.c')
| -rw-r--r-- | src/soc/intel/jasperlake/cpu.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c index ed9cfe703c..99cbef2e63 100644 --- a/src/soc/intel/jasperlake/cpu.c +++ b/src/soc/intel/jasperlake/cpu.c @@ -210,4 +210,7 @@ void soc_init_cpus(struct bus *cpu_bus) { if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); + + /* Thermal throttle activation offset */ + configure_tcc_thermal_target(); } |