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| author | Aamir Bohra <aamir.bohra@intel.com> | 2020-03-25 13:20:34 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-03-28 14:08:23 +0000 |
| commit | 512b77abb582e6c2566d3873b273dd32731e7bae (patch) | |
| tree | 8807f78791588d361bd1cef00e11f6619203c713 /src/soc/intel/jasperlake/espi.c | |
| parent | dd7acaad27e4f99f025df7f06d71dbb49d0e399b (diff) | |
| download | coreboot-512b77abb582e6c2566d3873b273dd32731e7bae.tar.xz | |
soc/intel/jasperlake: Remove Tiger Lake SoC code from Jasper Lake
This is a follow-up patch to initial copy patch for Jasper Lake SoC.
Remove all Tiger Lake specfic code from Jasper Lake SoC code.
BUG=b:150217037
Change-Id: I44dc6bf55ca18a3f0c350f5c3e9fae2996958648
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39824
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/jasperlake/espi.c')
| -rw-r--r-- | src/soc/intel/jasperlake/espi.c | 28 |
1 files changed, 2 insertions, 26 deletions
diff --git a/src/soc/intel/jasperlake/espi.c b/src/soc/intel/jasperlake/espi.c index da36ea6304..500644e104 100644 --- a/src/soc/intel/jasperlake/espi.c +++ b/src/soc/intel/jasperlake/espi.c @@ -12,12 +12,6 @@ * GNU General Public License for more details. */ -/* - * This file is created based on Intel Tiger Lake Processor PCH Datasheet - * Document number: 575857 - * Chapter number: 2 - */ - #include <device/device.h> #include <device/pci.h> #include <pc80/isa-dma.h> @@ -41,14 +35,14 @@ * certain memory range as reserved range for BIOS usage. * For this SOC, the range will be from 0FC800000h till FE7FFFFFh" */ -static const struct lpc_mmio_range tgl_lpc_fixed_mmio_ranges[] = { +static const struct lpc_mmio_range jsl_lpc_fixed_mmio_ranges[] = { { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, { 0, 0 } }; const struct lpc_mmio_range *soc_get_fixed_mmio_ranges() { - return tgl_lpc_fixed_mmio_ranges; + return jsl_lpc_fixed_mmio_ranges; } void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) @@ -70,24 +64,6 @@ void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec) pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]); } -uint8_t get_pch_series(void) -{ - uint16_t lpc_did_hi_byte; - - /* - * Fetch upper 8 bits on ESPI device ID to determine PCH type - * Adding 1 to the offset to fetch upper 8 bits - */ - lpc_did_hi_byte = pci_read_config8(PCH_DEV_ESPI, PCI_DEVICE_ID + 1); - - if (lpc_did_hi_byte == 0xA0) - return PCH_TGP; - else if (lpc_did_hi_byte == 0x4d) - return PCH_JSP; - else - return PCH_UNKNOWN_SERIES; -} - #if ENV_RAMSTAGE static void soc_mirror_dmi_pcr_io_dec(void) { |