diff options
| author | Aamir Bohra <aamir.bohra@intel.com> | 2020-03-25 11:36:22 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-03-28 14:08:04 +0000 |
| commit | dd7acaad27e4f99f025df7f06d71dbb49d0e399b (patch) | |
| tree | bee8d6993bdb992ef999de29df6303299dd4a04e /src/soc/intel/jasperlake/include | |
| parent | 18fd26cb088560fe31c3a569eefe2638ed071fc9 (diff) | |
| download | coreboot-dd7acaad27e4f99f025df7f06d71dbb49d0e399b.tar.xz | |
soc/intel/jasperlake: Add Jasper Lake SoC support
This is a copy patch from Tiger Lake SoC code.
The only changes done on top of copy is changing below configs:
1. SOC_INTEL_TIGERLAKE -> SOC_INTEL_TIGERLAKE_COPY
2. SOC_INTEL_JASPERLAKE -> SOC_INTEL_JASPERLAKE_COPY
3. SOC_INTEL_TIGERLAKE_BASE -> SOC_INTEL_TIGERLAKE_BASE_COPY
We started with initial assumption that JSL and TGL can co-exist.
But now we see the SoC code in Tiger Lake is relying on too many
compile-time directives to make two SoCs co-exist. Some of the
differences are listed below:
-> Kconfig: Multiple Kconfig options using
if SOC_INTEL_{TIGERLAKE/JASPERLAKE}
-> GPIO: GPIO communities have their own differences.
This requires conditional checks in gpio.asl, gpio.c, gpio*.h,
pmc.h and gpio.asl
-> PCI IRQs: Set up differently for JSL and TGL
-> PCIe: Number of Root ports differ.
-> eMMC/SD: Only supported on JSL.
-> USB: Number of USB port are different for JSL and TGL.
-> Memory configuration parameters are different for JSL and TGL.
-> FSP parameters for JSL and TGL are different.
The split of JSL and TGL SoC code is planned as below:
1. Copy Tiger Lake SoC code as is, and change SoC Kconfig
to avoid conflicts with current mainboard builds.
2. Clean up TGL code out of copy patch done in step 1.
Make it JSL only code. The SoC config still kept as
SOC_INTEL_JASPERLAKE_COPY.
3. Change JSL SOC Kconfig from SOC_INTEL_JASPERLAKE_COPY to
SOC_INTEL_JASPERLAKE, dedede and jasperlake_rvp boards can
bind to SoC code from soc/intel/jasperlake. This step establishes
Jasper Lake as a separate SoC.
4. Clean up current JSL code from TGL code. This step establishes
Tiger Lake as a separate SoC.
BUG=b:150217037
Change-Id: I9c33f478a2f8ed5e2d8e7815821d13044d35d388
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/soc/intel/jasperlake/include')
34 files changed, 3396 insertions, 0 deletions
diff --git a/src/soc/intel/jasperlake/include/soc/bootblock.h b/src/soc/intel/jasperlake/include/soc/bootblock.h new file mode 100644 index 0000000000..0c8d8c201a --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/bootblock.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TIGERLAKE_BOOTBLOCK_H_ +#define _SOC_TIGERLAKE_BOOTBLOCK_H_ + +/* Bootblock pre console init programming */ +void bootblock_cpu_init(void); +void bootblock_pch_early_init(void); + +/* Bootblock post console init programming */ +void pch_init(void); +void pch_early_iorange_init(void); +void report_platform_info(void); + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/cpu.h b/src/soc/intel/jasperlake/include/soc/cpu.h new file mode 100644 index 0000000000..799382498b --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/cpu.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TIGERLAKE_CPU_H_ +#define _SOC_TIGERLAKE_CPU_H_ + +#include <intelblocks/msr.h> + +/* Latency times in units of 32768ns */ +#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x9d +#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x9d +#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x9d +#define C_STATE_LATENCY_CONTROL_3_LIMIT 0x9d +#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x9d +#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x9d + +/* Power in units of mW */ +#define C1_POWER 0x3e8 +#define C6_POWER 0x15e +#define C7_POWER 0xc8 +#define C8_POWER 0xc8 +#define C9_POWER 0xc8 +#define C10_POWER 0xc8 + +/* Common Timer Copy (CTC) frequency - 38.4MHz. */ +#define CTC_FREQ 38400000 + +#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ + (((1 << ((base)*5)) * (limit)) / 1000) +#define C_STATE_LATENCY_FROM_LAT_REG(reg) \ + C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ + (IRTL_1024_NS >> 10)) + +/* Configure power limits for turbo mode */ +void set_power_limits(u8 power_limit_1_time); + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/espi.h b/src/soc/intel/jasperlake/include/soc/espi.h new file mode 100644 index 0000000000..3f7e32a717 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/espi.h @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 2 + */ + +#ifndef _SOC_TIGERLAKE_ESPI_H_ +#define _SOC_TIGERLAKE_ESPI_H_ + +#include <stdint.h> + +/* PCI Configuration Space (D31:F0): ESPI */ +#define SCI_IRQ_SEL (7 << 0) +#define SCIS_IRQ9 0 +#define SCIS_IRQ10 1 +#define SCIS_IRQ11 2 +#define SCIS_IRQ20 4 +#define SCIS_IRQ21 5 +#define SCIS_IRQ22 6 +#define SCIS_IRQ23 7 +#define SERIRQ_CNTL 0x64 +#define ESPI_IO_DEC 0x80 /* IO Decode Ranges Register */ +#define COMA_RANGE 0x0 /* 0x3F8 - 0x3FF COM1*/ +#define COMB_RANGE 0x1 /* 0x2F8 - 0x2FF COM2*/ +#define ESPI_GEN1_DEC 0x84 /* ESPI IF Generic Decode Range 1 */ +#define ESPI_GEN2_DEC 0x88 /* ESPI IF Generic Decode Range 2 */ +#define ESPI_GEN3_DEC 0x8c /* ESPI IF Generic Decode Range 3 */ +#define ESPI_GEN4_DEC 0x90 /* ESPI IF Generic Decode Range 4 */ +#define LGMR 0x98 /* ESPI Generic Memory Range */ +#define PCCTL 0xE0 /* PCI Clock Control */ +#define CLKRUN_EN (1 << 0) + +/* + * This function will help to differentiate between 2 PCH on single type of soc. + * Since same soc may have LP series pch or H series PCH, we need to + * differentiate by reading upper 8 bits of PCH device ids. + * + * Return: + * Return PCH_LP or PCH_H macro in case of respective device ID found. + * PCH_UNKNOWN_SERIES in case of invalid device ID. + */ +uint8_t get_pch_series(void); + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/gpe.h b/src/soc/intel/jasperlake/include/soc/gpe.h new file mode 100644 index 0000000000..c37750b1c4 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/gpe.h @@ -0,0 +1,133 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_GPE_H_ +#define _SOC_GPE_H_ + +/* GPE_31_0 */ +#define GPE0_DW0_00 0 +#define GPE0_DW0_01 1 +#define GPE0_DW0_02 2 +#define GPE0_DW0_03 3 +#define GPE0_DW0_04 4 +#define GPE0_DW0_05 5 +#define GPE0_DW0_06 6 +#define GPE0_DW0_07 7 +#define GPE0_DW0_08 8 +#define GPE0_DW0_09 9 +#define GPE0_DW0_10 10 +#define GPE0_DW0_11 11 +#define GPE0_DW0_12 12 +#define GPE0_DW0_13 13 +#define GPE0_DW0_14 14 +#define GPE0_DW0_15 15 +#define GPE0_DW0_16 16 +#define GPE0_DW0_17 17 +#define GPE0_DW0_18 18 +#define GPE0_DW0_19 19 +#define GPE0_DW0_20 20 +#define GPE0_DW0_21 21 +#define GPE0_DW0_22 22 +#define GPE0_DW0_23 23 +#define GPE0_DW0_24 24 +#define GPE0_DW0_25 25 +#define GPE0_DW0_26 26 +#define GPE0_DW0_27 27 +#define GPE0_DW0_28 28 +#define GPE0_DW0_29 29 +#define GPE0_DW0_30 30 +#define GPE0_DW0_31 31 +/* GPE_63_32 */ +#define GPE0_DW1_00 32 +#define GPE0_DW1_01 33 +#define GPE0_DW1_02 34 +#define GPE0_DW1_03 36 +#define GPE0_DW1_04 36 +#define GPE0_DW1_05 37 +#define GPE0_DW1_06 38 +#define GPE0_DW1_07 39 +#define GPE0_DW1_08 40 +#define GPE0_DW1_09 41 +#define GPE0_DW1_10 42 +#define GPE0_DW1_11 43 +#define GPE0_DW1_12 44 +#define GPE0_DW1_13 45 +#define GPE0_DW1_14 46 +#define GPE0_DW1_15 47 +#define GPE0_DW1_16 48 +#define GPE0_DW1_17 49 +#define GPE0_DW1_18 50 +#define GPE0_DW1_19 51 +#define GPE0_DW1_20 52 +#define GPE0_DW1_21 53 +#define GPE0_DW1_22 54 +#define GPE0_DW1_23 55 +#define GPE0_DW1_24 56 +#define GPE0_DW1_25 57 +#define GPE0_DW1_26 58 +#define GPE0_DW1_27 59 +#define GPE0_DW1_28 60 +#define GPE0_DW1_29 61 +#define GPE0_DW1_30 62 +#define GPE0_DW1_31 63 +/* GPE_95_64 */ +#define GPE0_DW2_00 64 +#define GPE0_DW2_01 65 +#define GPE0_DW2_02 66 +#define GPE0_DW2_03 67 +#define GPE0_DW2_04 68 +#define GPE0_DW2_05 69 +#define GPE0_DW2_06 70 +#define GPE0_DW2_07 71 +#define GPE0_DW2_08 72 +#define GPE0_DW2_09 73 +#define GPE0_DW2_10 74 +#define GPE0_DW2_11 75 +#define GPE0_DW2_12 76 +#define GPE0_DW2_13 77 +#define GPE0_DW2_14 78 +#define GPE0_DW2_15 79 +#define GPE0_DW2_16 80 +#define GPE0_DW2_17 81 +#define GPE0_DW2_18 82 +#define GPE0_DW2_19 83 +#define GPE0_DW2_20 84 +#define GPE0_DW2_21 85 +#define GPE0_DW2_22 86 +#define GPE0_DW2_23 87 +#define GPE0_DW2_24 88 +#define GPE0_DW2_25 89 +#define GPE0_DW2_26 90 +#define GPE0_DW2_27 91 +#define GPE0_DW2_28 92 +#define GPE0_DW2_29 93 +#define GPE0_DW2_30 94 +#define GPE0_DW2_31 95 +/* GPE_STD */ +#define GPE0_HOT_PLUG 97 +#define GPE0_SWGPE 98 +#define GPE0_TCOSCI 102 +#define GPE0_SMB_WAK 103 +#define GPE0_PCI_EXP 105 +#define GPE0_BATLOW 106 +#define GPE0_PME 107 +#define GPE0_ME_SCI 108 +#define GPE0_PME_B0 109 +#define GPE0_ESPI 110 +#define GPE0_GPIO_T2 111 +#define GPE0_LAN_WAK 112 +#define GPE0_WADT 114 + +#define GPE_MAX GPE0_WADT +#endif /* _SOC_GPE_H_ */ diff --git a/src/soc/intel/jasperlake/include/soc/gpio.h b/src/soc/intel/jasperlake/include/soc/gpio.h new file mode 100644 index 0000000000..fb3f42fd67 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/gpio.h @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TIGERLAKE_GPIO_H_ +#define _SOC_TIGERLAKE_GPIO_H_ + +#include <soc/gpio_defs.h> +#include <intelblocks/gpio.h> + +#if CONFIG(SOC_INTEL_TIGERLAKE_COPY) + + #define CROS_GPIO_NAME "INT34C5" + #define CROS_GPIO_COMM0_NAME "INT34C5:00" + #define CROS_GPIO_COMM1_NAME "INT34C5:01" + #define CROS_GPIO_COMM4_NAME "INT34C5:02" + #define CROS_GPIO_COMM5_NAME "INT34C5:03" + +#elif CONFIG(SOC_INTEL_JASPERLAKE_COPY) + + #define CROS_GPIO_NAME "INT34C8" + #define CROS_GPIO_COMM0_NAME "INT34C8:00" + #define CROS_GPIO_COMM1_NAME "INT34C8:01" + #define CROS_GPIO_COMM4_NAME "INT34C8:02" + #define CROS_GPIO_COMM5_NAME "INT34C8:03" +#endif + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/gpio_defs.h b/src/soc/intel/jasperlake/include/soc/gpio_defs.h new file mode 100644 index 0000000000..2898c12ee0 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/gpio_defs.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TIGERLAKE_GPIO_DEFS_H_ +#define _SOC_TIGERLAKE_GPIO_DEFS_H_ + +#if CONFIG(SOC_INTEL_TIGERLAKE_COPY) + #include <soc/gpio_defs_tgl.h> +#elif CONFIG(SOC_INTEL_JASPERLAKE_COPY) + #include <soc/gpio_defs_jsl.h> +#endif +#endif diff --git a/src/soc/intel/jasperlake/include/soc/gpio_defs_jsl.h b/src/soc/intel/jasperlake/include/soc/gpio_defs_jsl.h new file mode 100644 index 0000000000..69ed539cae --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/gpio_defs_jsl.h @@ -0,0 +1,272 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_JASPERLAKE_GPIO_DEFS_H_ +#define _SOC_JASPERLAKE_GPIO_DEFS_H_ + +#ifndef __ACPI__ +#include <stddef.h> +#endif +#include <soc/gpio_soc_defs_jsl.h> + + +#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ + +#define NUM_GPIO_COMx_GPI_REGS(n) \ + (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) + +#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS) +#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS) +#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS) +#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS) +#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS) + +#define NUM_GPI_STATUS_REGS \ + ((NUM_GPIO_COM0_GPI_REGS) +\ + (NUM_GPIO_COM1_GPI_REGS) +\ + (NUM_GPIO_COM2_GPI_REGS) +\ + (NUM_GPIO_COM4_GPI_REGS) +\ + (NUM_GPIO_COM5_GPI_REGS)) +/* + * IOxAPIC IRQs for the GPIOs + */ + +/* Group F */ +#define GPP_F0_IRQ 0x40 +#define GPP_F1_IRQ 0x41 +#define GPP_F2_IRQ 0x42 +#define GPP_F3_IRQ 0x43 +#define GPP_F4_IRQ 0x44 +#define GPP_F5_IRQ 0x45 +#define GPP_F6_IRQ 0x46 +#define GPP_F7_IRQ 0x47 +#define GPP_F8_IRQ 0x48 +#define GPP_F9_IRQ 0x49 +#define GPP_F10_IRQ 0x4a +#define GPP_F11_IRQ 0x4b +#define GPP_F12_IRQ 0x4c +#define GPP_F13_IRQ 0x4d +#define GPP_F14_IRQ 0x4e +#define GPP_F15_IRQ 0x4f +#define GPP_F16_IRQ 0x50 +#define GPP_F17_IRQ 0x51 +#define GPP_F18_IRQ 0x52 +#define GPP_F19_IRQ 0x53 + +/* Group G */ +#define GPP_G0_IRQ 0x18 +#define GPP_G1_IRQ 0x19 +#define GPP_G2_IRQ 0x1a +#define GPP_G3_IRQ 0x1b +#define GPP_G4_IRQ 0x1c +#define GPP_G5_IRQ 0x1d +#define GPP_G6_IRQ 0x1e +#define GPP_G7_IRQ 0x1f + +/* Group B */ +#define GPP_B0_IRQ 0x20 +#define GPP_B1_IRQ 0x21 +#define GPP_B2_IRQ 0x22 +#define GPP_B3_IRQ 0x23 +#define GPP_B4_IRQ 0x24 +#define GPP_B5_IRQ 0x25 +#define GPP_B6_IRQ 0x26 +#define GPP_B7_IRQ 0x27 +#define GPP_B8_IRQ 0x28 +#define GPP_B9_IRQ 0x29 +#define GPP_B10_IRQ 0x2a +#define GPP_B11_IRQ 0x2b +#define GPP_B12_IRQ 0x2c +#define GPP_B13_IRQ 0x2d +#define GPP_B14_IRQ 0x2e +#define GPP_B15_IRQ 0x2f +#define GPP_B16_IRQ 0x30 +#define GPP_B17_IRQ 0x31 +#define GPP_B18_IRQ 0x32 +#define GPP_B19_IRQ 0x33 +#define GPP_B20_IRQ 0x34 +#define GPP_B21_IRQ 0x35 +#define GPP_B22_IRQ 0x36 +#define GPP_B23_IRQ 0x37 + +/* Group A */ +#define GPP_A0_IRQ 0x38 +#define GPP_A1_IRQ 0x39 +#define GPP_A2_IRQ 0x3a +#define GPP_A3_IRQ 0x3b +#define GPP_A4_IRQ 0x3c +#define GPP_A5_IRQ 0x3d +#define GPP_A6_IRQ 0x3e +#define GPP_A7_IRQ 0x3f +#define GPP_A8_IRQ 0x40 +#define GPP_A9_IRQ 0x41 +#define GPP_A10_IRQ 0x42 +#define GPP_A11_IRQ 0x43 +#define GPP_A12_IRQ 0x44 +#define GPP_A13_IRQ 0x45 +#define GPP_A14_IRQ 0x46 +#define GPP_A15_IRQ 0x47 +#define GPP_A16_IRQ 0x48 +#define GPP_A17_IRQ 0x49 +#define GPP_A18_IRQ 0x4a +#define GPP_A19_IRQ 0x4b + +/* Group H */ +#define GPP_H0_IRQ 0x70 +#define GPP_H1_IRQ 0x71 +#define GPP_H2_IRQ 0x72 +#define GPP_H3_IRQ 0x73 +#define GPP_H4_IRQ 0x74 +#define GPP_H5_IRQ 0x75 +#define GPP_H6_IRQ 0x76 +#define GPP_H7_IRQ 0x77 +#define GPP_H8_IRQ 0x18 +#define GPP_H9_IRQ 0x19 +#define GPP_H10_IRQ 0x1a +#define GPP_H11_IRQ 0x1b +#define GPP_H12_IRQ 0x1c +#define GPP_H13_IRQ 0x1d +#define GPP_H14_IRQ 0x1e +#define GPP_H15_IRQ 0x1f +#define GPP_H16_IRQ 0x20 +#define GPP_H17_IRQ 0x21 +#define GPP_H18_IRQ 0x22 +#define GPP_H19_IRQ 0x23 +#define GPP_H20_IRQ 0x24 +#define GPP_H21_IRQ 0x25 +#define GPP_H22_IRQ 0x26 +#define GPP_H23_IRQ 0x27 + +/* Group D */ +#define GPP_D0_IRQ 0x28 +#define GPP_D1_IRQ 0x29 +#define GPP_D2_IRQ 0x2a +#define GPP_D3_IRQ 0x2b +#define GPP_D4_IRQ 0x2c +#define GPP_D5_IRQ 0x2d +#define GPP_D6_IRQ 0x2e +#define GPP_D7_IRQ 0x2f +#define GPP_D8_IRQ 0x30 +#define GPP_D9_IRQ 0x31 +#define GPP_D10_IRQ 0x32 +#define GPP_D11_IRQ 0x33 +#define GPP_D12_IRQ 0x34 +#define GPP_D13_IRQ 0x35 +#define GPP_D14_IRQ 0x36 +#define GPP_D15_IRQ 0x37 +#define GPP_D16_IRQ 0x38 +#define GPP_D17_IRQ 0x39 +#define GPP_D18_IRQ 0x3a +#define GPP_D19_IRQ 0x3b +#define GPP_D20_IRQ 0x3c +#define GPP_D21_IRQ 0x3d +#define GPP_D22_IRQ 0x3e +#define GPP_D23_IRQ 0x3f + +/* Group GPD */ +#define GPD0_IRQ 0x64 +#define GPD1_IRQ 0x65 +#define GPD2_IRQ 0x66 +#define GPD3_IRQ 0x67 +#define GPD4_IRQ 0x68 +#define GPD5_IRQ 0x69 +#define GPD6_IRQ 0x6a +#define GPD7_IRQ 0x6b +#define GPD8_IRQ 0x6c +#define GPD9_IRQ 0x6d +#define GPD10_IRQ 0x6e + +/* Group C */ +#define GPP_C0_IRQ 0x5a +#define GPP_C1_IRQ 0x5b +#define GPP_C2_IRQ 0x5c +#define GPP_C3_IRQ 0x5d +#define GPP_C4_IRQ 0x5e +#define GPP_C5_IRQ 0x5f +#define GPP_C6_IRQ 0x60 +#define GPP_C7_IRQ 0x61 +#define GPP_C8_IRQ 0x62 +#define GPP_C9_IRQ 0x63 +#define GPP_C10_IRQ 0x64 +#define GPP_C11_IRQ 0x65 +#define GPP_C12_IRQ 0x66 +#define GPP_C13_IRQ 0x67 +#define GPP_C14_IRQ 0x68 +#define GPP_C15_IRQ 0x69 +#define GPP_C16_IRQ 0x6a +#define GPP_C17_IRQ 0x6b +#define GPP_C18_IRQ 0x6c +#define GPP_C19_IRQ 0x6d +#define GPP_C20_IRQ 0x6e +#define GPP_C21_IRQ 0x6f +#define GPP_C22_IRQ 0x70 +#define GPP_C23_IRQ 0x71 +/* Group E */ +#define GPP_E0_IRQ 0x72 +#define GPP_E1_IRQ 0x73 +#define GPP_E2_IRQ 0x74 +#define GPP_E3_IRQ 0x75 +#define GPP_E4_IRQ 0x76 +#define GPP_E5_IRQ 0x77 +#define GPP_E6_IRQ 0x18 +#define GPP_E7_IRQ 0x19 +#define GPP_E8_IRQ 0x1a +#define GPP_E9_IRQ 0x1b +#define GPP_E10_IRQ 0x1c +#define GPP_E11_IRQ 0x1d +#define GPP_E12_IRQ 0x1e +#define GPP_E13_IRQ 0x1f +#define GPP_E14_IRQ 0x20 +#define GPP_E15_IRQ 0x21 +#define GPP_E16_IRQ 0x22 +#define GPP_E17_IRQ 0x23 +#define GPP_E18_IRQ 0x24 +#define GPP_E19_IRQ 0x25 +#define GPP_E20_IRQ 0x26 +#define GPP_E21_IRQ 0x27 +#define GPP_E22_IRQ 0x28 +#define GPP_E23_IRQ 0x29 + +/* Group R*/ +#define GPP_R0_IRQ 0x50 +#define GPP_R1_IRQ 0x51 +#define GPP_R2_IRQ 0x52 +#define GPP_R3_IRQ 0x53 +#define GPP_R4_IRQ 0x54 +#define GPP_R5_IRQ 0x55 +#define GPP_R6_IRQ 0x56 +#define GPP_R7_IRQ 0x57 + +/* Group S */ +#define GPP_S0_IRQ 0x5c +#define GPP_S1_IRQ 0x5d +#define GPP_S2_IRQ 0x5e +#define GPP_S3_IRQ 0x5f +#define GPP_S4_IRQ 0x60 +#define GPP_S5_IRQ 0x61 +#define GPP_S6_IRQ 0x62 +#define GPP_S7_IRQ 0x63 + +/* Register defines. */ +#define GPIO_MISCCFG 0x10 +#define GPE_DW_SHIFT 8 +#define GPE_DW_MASK 0xfff00 +#define HOSTSW_OWN_REG_0 0xc0 +#define GPI_INT_STS_0 0x100 +#define GPI_INT_EN_0 0x120 +#define GPI_SMI_STS_0 0x180 +#define GPI_SMI_EN_0 0x1a0 +#define PAD_CFG_BASE 0x600 + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/gpio_defs_tgl.h b/src/soc/intel/jasperlake/include/soc/gpio_defs_tgl.h new file mode 100644 index 0000000000..35a15ded66 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/gpio_defs_tgl.h @@ -0,0 +1,314 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TIGERLAKE_GPIO_DEFS_TGL_H_ +#define _SOC_TIGERLAKE_GPIO_DEFS_TGL_H_ + +#ifndef __ACPI__ +#include <stddef.h> +#endif +#include <soc/gpio_soc_defs.h> + +#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ + +#define NUM_GPIO_COMx_GPI_REGS(n) \ + (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) + +#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS) +#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS) +#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS) +#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS) +#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS) + +#define NUM_GPI_STATUS_REGS \ + ((NUM_GPIO_COM0_GPI_REGS) +\ + (NUM_GPIO_COM1_GPI_REGS) +\ + (NUM_GPIO_COM2_GPI_REGS) +\ + (NUM_GPIO_COM4_GPI_REGS) +\ + (NUM_GPIO_COM5_GPI_REGS)) +/* + * IOxAPIC IRQs for the GPIOs + */ + +/* Group B */ +#define GPP_B0_IRQ 0x18 +#define GPP_B1_IRQ 0x19 +#define GPP_B2_IRQ 0x1A +#define GPP_B3_IRQ 0x1B +#define GPP_B4_IRQ 0x1C +#define GPP_B5_IRQ 0x1D +#define GPP_B6_IRQ 0x1E +#define GPP_B7_IRQ 0x1F +#define GPP_B8_IRQ 0x20 +#define GPP_B9_IRQ 0x21 +#define GPP_B10_IRQ 0x22 +#define GPP_B11_IRQ 0x23 +#define GPP_B12_IRQ 0x24 +#define GPP_B13_IRQ 0x25 +#define GPP_B14_IRQ 0x26 +#define GPP_B15_IRQ 0x27 +#define GPP_B16_IRQ 0x28 +#define GPP_B17_IRQ 0x29 +#define GPP_B18_IRQ 0x2A +#define GPP_B19_IRQ 0x2B +#define GPP_B20_IRQ 0x2C +#define GPP_B21_IRQ 0x2D +#define GPP_B22_IRQ 0x2E +#define GPP_B23_IRQ 0x2F + +/* Group T */ +#define GPP_T0_IRQ 0x30 +#define GPP_T1_IRQ 0x31 +#define GPP_T2_IRQ 0x32 +#define GPP_T3_IRQ 0x33 +#define GPP_T4_IRQ 0x34 +#define GPP_T5_IRQ 0x35 +#define GPP_T6_IRQ 0x36 +#define GPP_T7_IRQ 0x37 +#define GPP_T8_IRQ 0x38 +#define GPP_T9_IRQ 0x39 +#define GPP_T10_IRQ 0x3A +#define GPP_T11IRQ 0x3B +#define GPP_T12_IRQ 0x3C +#define GPP_T13_IRQ 0x3D +#define GPP_T14_IRQ 0x3E +#define GPP_T15_IRQ 0x3F + +/* Group A */ +#define GPP_A0_IRQ 0x40 +#define GPP_A1_IRQ 0x41 +#define GPP_A2_IRQ 0x42 +#define GPP_A3_IRQ 0x43 +#define GPP_A4_IRQ 0x44 +#define GPP_A5_IRQ 0x45 +#define GPP_A6_IRQ 0x46 +#define GPP_A7_IRQ 0x47 +#define GPP_A8_IRQ 0x48 +#define GPP_A9_IRQ 0x49 +#define GPP_A10_IRQ 0x4A +#define GPP_A11_IRQ 0x4B +#define GPP_A12_IRQ 0x4C +#define GPP_A13_IRQ 0x4D +#define GPP_A14_IRQ 0x4E +#define GPP_A15_IRQ 0x4F +#define GPP_A16_IRQ 0x50 +#define GPP_A17_IRQ 0x51 +#define GPP_A18_IRQ 0x52 +#define GPP_A19_IRQ 0x53 +#define GPP_A20_IRQ 0x54 +#define GPP_A21_IRQ 0x55 +#define GPP_A22_IRQ 0x56 +#define GPP_A23_IRQ 0x57 + +/* Group R */ +#define GPP_R0_IRQ 0x58 +#define GPP_R1_IRQ 0x59 +#define GPP_R2_IRQ 0x5A +#define GPP_R3_IRQ 0x5B +#define GPP_R4_IRQ 0x5C +#define GPP_R5_IRQ 0x5D +#define GPP_R6_IRQ 0x5E +#define GPP_R7_IRQ 0x5F + + +/* Group D */ +#define GPD0_IRQ 0x60 +#define GPD1_IRQ 0x61 +#define GPD2_IRQ 0x62 +#define GPD3_IRQ 0x63 +#define GPD4_IRQ 0x64 +#define GPD5_IRQ 0x65 +#define GPD6_IRQ 0x66 +#define GPD7_IRQ 0x67 +#define GPD8_IRQ 0x68 +#define GPD9_IRQ 0x69 +#define GPD10_IRQ 0x6A +#define GPD11_IRQ 0x6B + +/* Group S */ +#define GPP_S0_IRQ 0x6C +#define GPP_S1_IRQ 0x6D +#define GPP_S2_IRQ 0x6E +#define GPP_S3_IRQ 0x6F +#define GPP_S4_IRQ 0x70 +#define GPP_S5_IRQ 0x71 +#define GPP_S6_IRQ 0x72 +#define GPP_S7_IRQ 0x73 + +/* Group H */ +#define GPP_H0_IRQ 0x74 +#define GPP_H1_IRQ 0x75 +#define GPP_H2_IRQ 0x76 +#define GPP_H3_IRQ 0x77 +#define GPP_H4_IRQ 0x18 +#define GPP_H5_IRQ 0x19 +#define GPP_H6_IRQ 0x1A +#define GPP_H7_IRQ 0x1B +#define GPP_H8_IRQ 0x1C +#define GPP_H9_IRQ 0x1D +#define GPP_H10_IRQ 0x1E +#define GPP_H11_IRQ 0x1F +#define GPP_H12_IRQ 0x20 +#define GPP_H13_IRQ 0x21 +#define GPP_H14_IRQ 0x22 +#define GPP_H15_IRQ 0x23 +#define GPP_H16_IRQ 0x24 +#define GPP_H17_IRQ 0x25 +#define GPP_H18_IRQ 0x26 +#define GPP_H19_IRQ 0x27 +#define GPP_H20_IRQ 0x28 +#define GPP_H21_IRQ 0x29 +#define GPP_H22_IRQ 0x2A +#define GPP_H23_IRQ 0x2B + +/* Group D */ +#define GPP_D0_IRQ 0x2C +#define GPP_D1_IRQ 0x2D +#define GPP_D2_IRQ 0x2E +#define GPP_D3_IRQ 0x2F +#define GPP_D4_IRQ 0x30 +#define GPP_D5_IRQ 0x31 +#define GPP_D6_IRQ 0x32 +#define GPP_D7_IRQ 0x33 +#define GPP_D8_IRQ 0x34 +#define GPP_D9_IRQ 0x35 +#define GPP_D10_IRQ 0x36 +#define GPP_D11_IRQ 0x37 +#define GPP_D12_IRQ 0x38 +#define GPP_D13_IRQ 0x39 +#define GPP_D14_IRQ 0x3A +#define GPP_D15_IRQ 0x3B +#define GPP_D16_IRQ 0x3C +#define GPP_D17_IRQ 0x3D +#define GPP_D18_IRQ 0x3E +#define GPP_D19_IRQ 0x3F + + +/* Group U */ +#define GPP_U0_IRQ 0x40 +#define GPP_U1IRQ 0x41 +#define GPP_U2_IRQ 0x42 +#define GPP_U3_IRQ 0x43 +#define GPP_U4_IRQ 0x44 +#define GPP_U5_IRQ 0x45 +#define GPP_U6_IRQ 0x46 +#define GPP_U7_IRQ 0x47 +#define GPP_U8_IRQ 0x48 +#define GPP_U9_IRQ 0x49 +#define GPP_U10_IRQ 0x4A +#define GPP_U11_IRQ 0x4B +#define GPP_U12_IRQ 0x4C +#define GPP_U13_IRQ 0x4D +#define GPP_U14_IRQ 0x4E +#define GPP_U15_IRQ 0x4F +#define GPP_U16_IRQ 0x50 +#define GPP_U17_IRQ 0x51 +#define GPP_U18_IRQ 0x52 +#define GPP_U19_IRQ 0x53 + + +#define GPP_VGPIO4_IRQ 0x54 + +/* Group F */ +#define GPP_F0_IRQ 0x56 +#define GPP_F1_IRQ 0x57 +#define GPP_F2_IRQ 0x58 +#define GPP_F3_IRQ 0x59 +#define GPP_F4_IRQ 0x5A +#define GPP_F5_IRQ 0x5B +#define GPP_F6_IRQ 0x5C +#define GPP_F7_IRQ 0x5D +#define GPP_F8_IRQ 0x5E +#define GPP_F9_IRQ 0x5F +#define GPP_F10_IRQ 0x60 +#define GPP_F11_IRQ 0x61 +#define GPP_F12_IRQ 0x62 +#define GPP_F13_IRQ 0x63 +#define GPP_F14_IRQ 0x64 +#define GPP_F15_IRQ 0x65 +#define GPP_F16_IRQ 0x66 +#define GPP_F17_IRQ 0x67 +#define GPP_F18_IRQ 0x68 +#define GPP_F19_IRQ 0x69 +#define GPP_F20_IRQ 0x6A +#define GPP_F21_IRQ 0x6B +#define GPP_F22_IRQ 0x6C +#define GPP_F23_IRQ 0x6D + +/* Group C */ +#define GPP_C0_iIRQ 0x6E +#define GPP_C1_IRQ 0x6F +#define GPP_C2_IRQ 0x70 +#define GPP_C3_IRQ 0x71 +#define GPP_C4_IRQ 0x72 +#define GPP_C5_IRQ 0x73 +#define GPP_C6_IRQ 0x74 +#define GPP_C7_IRQ 0x75 +#define GPP_C8_IRQ 0x76 +#define GPP_C9_IRQ 0x77 +#define GPP_C10_IRQ 0x18 +#define GPP_C11_IRQ 0x19 +#define GPP_C12_IRQ 0x1A +#define GPP_C13_IRQ 0x1B +#define GPP_C14_IRQ 0x1C +#define GPP_C15_IRQ 0x1D +#define GPP_C16_IRQ 0x1E +#define GPP_C17_IRQ 0x1F +#define GPP_C18_IRQ 0x20 +#define GPP_C19_IRQ 0x21 +#define GPP_C20_IRQ 0x22 +#define GPP_C21_IRQ 0x23 +#define GPP_C22_IRQ 0x24 +#define GPP_C23_IRQ 0x25 + + + +/* Group E */ +#define GPP_E0_IRQ 0x26 +#define GPP_E1_IRQ 0x27 +#define GPP_E2_IRQ 0x28 +#define GPP_E3_IRQ 0x29 +#define GPP_E4_IRQ 0x30 +#define GPP_E5_IRQ 0x31 +#define GPP_E6_IRQ 0x32 +#define GPP_E7_IRQ 0x33 +#define GPP_E8_IRQ 0x34 +#define GPP_E9_IRQ 0x35 +#define GPP_E10_IRQ 0x36 +#define GPP_E11_IRQ 0x37 +#define GPP_E12_IRQ 0x38 +#define GPP_E13_IRQ 0x39 +#define GPP_E14_IRQ 0x3A +#define GPP_E15_IRQ 0x3B +#define GPP_E16_IRQ 0x3C +#define GPP_E17_IRQ 0x3D +#define GPP_E18_IRQ 0x3E +#define GPP_E19_IRQ 0x3F +#define GPP_E20_IRQ 0x40 +#define GPP_E21_IRQ 0x41 +#define GPP_E22_IRQ 0x42 +#define GPP_E23_IRQ 0x43 + +/* Register defines. */ +#define GPIO_MISCCFG 0x10 +#define GPE_DW_SHIFT 8 +#define GPE_DW_MASK 0xfff00 +#define HOSTSW_OWN_REG_0 0xb0 +#define GPI_INT_STS_0 0x100 +#define GPI_INT_EN_0 0x110 +#define GPI_SMI_STS_0 0x180 +#define GPI_SMI_EN_0 0x1A0 +#define PAD_CFG_BASE 0x700 + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h b/src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h new file mode 100644 index 0000000000..b3ab9c3b5b --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef _SOC_TIGERLAKE_GPIO_SOC_DEFS_H_ +#define _SOC_TIGERLAKE_GPIO_SOC_DEFS_H_ + +#if CONFIG(SOC_INTEL_TIGERLAKE_COPY) + #include "gpio_soc_defs_tgl.h" +#elif CONFIG(SOC_INTEL_JASPERLAKE_COPY) + #include "gpio_soc_defs_jsl.h" +#endif + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/gpio_soc_defs_jsl.h b/src/soc/intel/jasperlake/include/soc/gpio_soc_defs_jsl.h new file mode 100644 index 0000000000..2ee52b260f --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/gpio_soc_defs_jsl.h @@ -0,0 +1,358 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_JASPERLAKE_GPIO_SOC_DEFS_JSL_H_ +#define _SOC_JASPERLAKE_GPIO_SOC_DEFS_JSL_H_ + +/* + * Most of the fixed numbers and macros are based on the GPP groups. + * The GPIO groups are accessed through register blocks called + * communities. + */ + +#define GPP_A 0x0 +#define GPP_B 0x1 +#define GPP_G 0x2 +#define GPP_C 0x3 +#define GPP_R 0x4 +#define GPP_D 0x5 +#define GPP_S 0x6 +#define GPP_H 0x7 +#define GPP_VGPIO 0x8 +#define GPP_F 0x9 +#define GPP_GPD 0xA +#define GPP_E 0xD + +#define GPIO_NUM_GROUPS 12 +#define GPIO_MAX_NUM_PER_GROUP 24 + +/* + * GPIOs are ordered monotonically increasing to match ACPI/OS driver. + */ + +/* Group F */ +#define GPP_F0 0 +#define GPP_F1 1 +#define GPP_F2 2 +#define GPP_F3 3 +#define GPP_F4 4 +#define GPP_F5 5 +#define GPP_F6 6 +#define GPP_F7 7 +#define GPP_F8 8 +#define GPP_F9 9 +#define GPP_F10 10 +#define GPP_F11 11 +#define GPP_F12 12 +#define GPP_F13 13 +#define GPP_F14 14 +#define GPP_F15 15 +#define GPP_F16 16 +#define GPP_F17 17 +#define GPP_F18 18 +#define GPP_F19 19 + +/* Group B */ +#define GPIO_RSVD_0 20 +#define GPIO_RSVD_1 21 +#define GPIO_RSVD_2 22 +#define GPIO_RSVD_3 23 +#define GPIO_RSVD_4 24 +#define GPIO_RSVD_5 25 +#define GPIO_RSVD_6 26 +#define GPIO_RSVD_7 27 +#define GPIO_RSVD_8 28 +#define GPP_B0 29 +#define GPP_B1 30 +#define GPP_B2 31 +#define GPP_B3 32 +#define GPP_B4 33 +#define GPP_B5 34 +#define GPP_B6 35 +#define GPP_B7 36 +#define GPP_B8 37 +#define GPP_B9 38 +#define GPP_B10 39 +#define GPP_B11 40 +#define GPP_B12 41 +#define GPP_B13 42 +#define GPP_B14 43 +#define GPP_B15 44 +#define GPP_B16 45 +#define GPP_B17 46 +#define GPP_B18 47 +#define GPP_B19 48 +#define GPP_B20 49 +#define GPP_B21 50 +#define GPP_B22 51 +#define GPP_B23 52 +#define GPIO_RSVD_9 53 +#define GPIO_RSVD_10 54 + +/* Group A */ +#define GPP_A0 55 +#define GPP_A1 56 +#define GPP_A2 57 +#define GPP_A3 58 +#define GPP_A4 59 +#define GPP_A5 60 +#define GPP_A6 61 +#define GPP_A7 62 +#define GPP_A8 63 +#define GPP_A9 64 +#define GPP_A10 65 +#define GPP_A11 66 +#define GPP_A12 67 +#define GPP_A13 68 +#define GPP_A14 69 +#define GPP_A15 70 +#define GPP_A16 71 +#define GPP_A17 72 +#define GPP_A18 73 +#define GPP_A19 74 +#define GPIO_RSVD_11 75 + +/* Group S */ +#define GPP_S0 76 +#define GPP_S1 77 +#define GPP_S2 78 +#define GPP_S3 79 +#define GPP_S4 80 +#define GPP_S5 81 +#define GPP_S6 82 +#define GPP_S7 83 + +/* Group R */ +#define GPP_R0 84 +#define GPP_R1 85 +#define GPP_R2 86 +#define GPP_R3 87 +#define GPP_R4 88 +#define GPP_R5 89 +#define GPP_R6 90 +#define GPP_R7 91 + +#define GPIO_COM0_START GPP_F0 +#define GPIO_COM0_END GPP_R7 +#define NUM_GPIO_COM0_PADS (GPIO_COM0_END - GPIO_COM0_START + 1) + +/* Group H */ +#define GPP_H0 92 +#define GPP_H1 93 +#define GPP_H2 94 +#define GPP_H3 95 +#define GPP_H4 96 +#define GPP_H5 97 +#define GPP_H6 98 +#define GPP_H7 99 +#define GPP_H8 100 +#define GPP_H9 101 +#define GPP_H10 102 +#define GPP_H11 103 +#define GPP_H12 104 +#define GPP_H13 105 +#define GPP_H14 106 +#define GPP_H15 107 +#define GPP_H16 108 +#define GPP_H17 109 +#define GPP_H18 110 +#define GPP_H19 111 +#define GPP_H20 112 +#define GPP_H21 113 +#define GPP_H22 114 +#define GPP_H23 115 + +/* Group D */ +#define GPP_D0 116 +#define GPP_D1 117 +#define GPP_D2 118 +#define GPP_D3 119 +#define GPP_D4 120 +#define GPP_D5 121 +#define GPP_D6 122 +#define GPP_D7 123 +#define GPP_D8 124 +#define GPP_D9 125 +#define GPP_D10 126 +#define GPP_D11 127 +#define GPP_D12 128 +#define GPP_D13 129 +#define GPP_D14 130 +#define GPP_D15 131 +#define GPP_D16 132 +#define GPP_D17 133 +#define GPP_D18 134 +#define GPP_D19 135 +#define GPP_D20 136 +#define GPP_D21 137 +#define GPP_D22 138 +#define GPP_D23 139 +#define GPIO_RSVD_12 140 +#define GPIO_RSVD_13 141 + +/* Group VGPIO */ +#define VGPIO_0 142 +#define VGPIO_3 143 +#define VGPIO_4 144 +#define VGPIO_5 145 +#define VGPIO_6 146 +#define VGPIO_7 147 +#define VGPIO_8 148 +#define VGPIO_9 149 +#define VGPIO_10 150 +#define VGPIO_11 151 +#define VGPIO_12 152 +#define VGPIO_13 153 +#define VGPIO_18 154 +#define VGPIO_19 155 +#define VGPIO_20 156 +#define VGPIO_21 157 +#define VGPIO_22 158 +#define VGPIO_23 159 +#define VGPIO_24 160 +#define VGPIO_25 161 +#define VGPIO_30 162 +#define VGPIO_31 163 +#define VGPIO_32 164 +#define VGPIO_33 165 +#define VGPIO_34 166 +#define VGPIO_35 167 +#define VGPIO_36 168 +#define VGPIO_37 169 +#define VGPIO_39 170 + +/* Group C */ +#define GPP_C0 171 +#define GPP_C1 172 +#define GPP_C2 173 +#define GPP_C3 174 +#define GPP_C4 175 +#define GPP_C5 176 +#define GPP_C6 177 +#define GPP_C7 178 +#define GPP_C8 179 +#define GPP_C9 180 +#define GPP_C10 181 +#define GPP_C11 182 +#define GPP_C12 183 +#define GPP_C13 184 +#define GPP_C14 185 +#define GPP_C15 186 +#define GPP_C16 187 +#define GPP_C17 188 +#define GPP_C18 189 +#define GPP_C19 190 +#define GPP_C20 191 +#define GPP_C21 192 +#define GPP_C22 193 +#define GPP_C23 194 + +#define GPIO_COM1_START GPP_H0 +#define GPIO_COM1_END GPP_C23 +#define NUM_GPIO_COM1_PADS (GPIO_COM1_END - GPIO_COM1_START + 1) + +/* Group GPD */ +#define GPD0 195 +#define GPD1 196 +#define GPD2 197 +#define GPD3 198 +#define GPD4 199 +#define GPD5 200 +#define GPD6 201 +#define GPD7 202 +#define GPD8 203 +#define GPD9 204 +#define GPD10 205 +#define GPIO_RSVD_14 206 +#define GPIO_RSVD_15 207 +#define GPIO_RSVD_16 208 +#define GPIO_RSVD_17 209 + +#define GPIO_COM2_START GPD0 +#define GPIO_COM2_END GPIO_RSVD_17 +#define NUM_GPIO_COM2_PADS (GPIO_COM2_END - GPIO_COM2_START + 1) + +/* Group E */ +#define GPIO_RSVD_18 210 +#define GPIO_RSVD_19 211 +#define GPIO_RSVD_20 212 +#define GPIO_RSVD_21 213 +#define GPIO_RSVD_22 214 +#define GPIO_RSVD_23 215 +#define GPP_E0 216 +#define GPP_E1 217 +#define GPP_E2 218 +#define GPP_E3 219 +#define GPP_E4 220 +#define GPP_E5 221 +#define GPP_E6 222 +#define GPP_E7 223 +#define GPP_E8 224 +#define GPP_E9 225 +#define GPP_E10 226 +#define GPP_E11 227 +#define GPP_E12 228 +#define GPP_E13 229 +#define GPP_E14 230 +#define GPP_E15 231 +#define GPP_E16 232 +#define GPP_E17 233 +#define GPP_E18 234 +#define GPP_E19 235 +#define GPP_E20 236 +#define GPP_E21 237 +#define GPP_E22 238 +#define GPP_E23 239 +#define GPIO_RSVD_24 240 +#define GPIO_RSVD_25 241 +#define GPIO_RSVD_26 242 +#define GPIO_RSVD_27 243 +#define GPIO_RSVD_28 244 +#define GPIO_RSVD_29 245 +#define GPIO_RSVD_30 246 +#define GPIO_RSVD_31 247 +#define GPIO_RSVD_32 248 +#define GPIO_RSVD_33 249 +#define GPIO_RSVD_34 250 +#define GPIO_RSVD_35 251 +#define GPIO_RSVD_36 252 + +#define GPIO_COM4_START GPIO_RSVD_18 +#define GPIO_COM4_END GPIO_RSVD_36 +#define NUM_GPIO_COM4_PADS (GPIO_COM4_END - GPIO_COM4_START + 1) + +/* Group G */ +#define GPP_G0 253 +#define GPP_G1 254 +#define GPP_G2 255 +#define GPP_G3 256 +#define GPP_G4 257 +#define GPP_G5 258 +#define GPP_G6 259 +#define GPP_G7 260 + +#define GPIO_COM5_START GPP_G0 +#define GPIO_COM5_END GPP_G7 +#define NUM_GPIO_COM5_PADS (GPIO_COM5_END - GPIO_COM5_START + 1) + +#define TOTAL_PADS 261 + +#define COMM_0 0 +#define COMM_1 1 +#define COMM_2 2 +#define COMM_4 3 +#define COMM_5 4 +#define TOTAL_GPIO_COMM 5 + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/gpio_soc_defs_tgl.h b/src/soc/intel/jasperlake/include/soc/gpio_soc_defs_tgl.h new file mode 100644 index 0000000000..ec582c3133 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/gpio_soc_defs_tgl.h @@ -0,0 +1,394 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef _SOC_TIGERLAKE_GPIO_SOC_DEFS_TGL_H_ +#define _SOC_TIGERLAKE_GPIO_SOC_DEFS_TGL_H_ +/* + * Most of the fixed numbers and macros are based on the GPP groups. + * The GPIO groups are accessed through register blocks called + * communities. + */ +#define GPP_B 0x0 +#define GPP_T 0x1 +#define GPP_A 0x2 +#define GPP_R 0x3 +#define GPD 0x4 +#define GPP_S 0x5 +#define GPP_H 0x6 +#define GPP_D 0x7 +#define GPP_U 0x8 +#define GPP_F 0xA +#define GPP_C 0xB +#define GPP_E 0xC + +#define GPIO_MAX_NUM_PER_GROUP 27 + +#define COMM_0 0 +#define COMM_1 1 +#define COMM_2 2 +/* GPIO community 3 is not exposed to be used and hence is skipped. */ +#define COMM_4 3 +#define COMM_5 4 +/* + * GPIOs are ordered monotonically increasing to match ACPI/OS driver. + */ +/* Group B */ +#define GPP_B0 0 +#define GPP_B1 1 +#define GPP_B2 2 +#define GPP_B3 3 +#define GPP_B4 4 +#define GPP_B5 5 +#define GPP_B6 6 +#define GPP_B7 7 +#define GPP_B8 8 +#define GPP_B9 9 +#define GPP_B10 10 +#define GPP_B11 11 +#define GPP_B12 12 +#define GPP_B13 13 +#define GPP_B14 14 +#define GPP_B15 15 +#define GPP_B16 16 +#define GPP_B17 17 +#define GPP_B18 18 +#define GPP_B19 19 +#define GPP_B20 20 +#define GPP_B21 21 +#define GPP_B22 22 +#define GPP_B23 23 +#define GPP_B24 24 /* GSPI0_CLK_LOOPBK */ +#define GPP_B25 25 /* GSPI1_CLK_LOOPBK */ + +/* Group T */ +#define GPP_T0 26 +#define GPP_T1 27 +#define GPP_T2 28 +#define GPP_T3 29 +#define GPP_T4 30 +#define GPP_T5 31 +#define GPP_T6 32 +#define GPP_T7 33 +#define GPP_T8 34 +#define GPP_T9 35 +#define GPP_T10 36 +#define GPP_T11 37 +#define GPP_T12 38 +#define GPP_T13 39 +#define GPP_T14 40 +#define GPP_T15 41 + +/* Group A */ +#define GPP_A0 42 +#define GPP_A1 43 +#define GPP_A2 44 +#define GPP_A3 45 +#define GPP_A4 46 +#define GPP_A5 47 +#define GPP_A6 48 +#define GPP_A7 49 +#define GPP_A8 50 +#define GPP_A9 51 +#define GPP_A10 52 +#define GPP_A11 53 +#define GPP_A12 54 +#define GPP_A13 55 +#define GPP_A14 56 +#define GPP_A15 57 +#define GPP_A16 58 +#define GPP_A17 59 +#define GPP_A18 60 +#define GPP_A19 61 +#define GPP_A20 62 +#define GPP_A21 63 +#define GPP_A22 64 +#define GPP_A23 65 +#define GPP_A24 66 /* ESPI_CLK_LOOPBK */ + +#define GPIO_COM0_START GPP_B0 +#define GPIO_COM0_END GPP_A24 +#define NUM_GPIO_COM0_PADS (GPP_A24 - GPP_B0 + 1) + +/* Group S */ +#define GPP_S0 67 +#define GPP_S1 68 +#define GPP_S2 69 +#define GPP_S3 70 +#define GPP_S4 71 +#define GPP_S5 72 +#define GPP_S6 73 +#define GPP_S7 74 + +/* Group H */ +#define GPP_H0 75 +#define GPP_H1 76 +#define GPP_H2 77 +#define GPP_H3 78 +#define GPP_H4 79 +#define GPP_H5 80 +#define GPP_H6 81 +#define GPP_H7 82 +#define GPP_H8 83 +#define GPP_H9 84 +#define GPP_H10 85 +#define GPP_H11 86 +#define GPP_H12 87 +#define GPP_H13 88 +#define GPP_H14 89 +#define GPP_H15 90 +#define GPP_H16 91 +#define GPP_H17 92 +#define GPP_H18 93 +#define GPP_H19 94 +#define GPP_H20 95 +#define GPP_H21 96 +#define GPP_H22 97 +#define GPP_H23 98 + +/* Group D */ +#define GPP_D0 99 +#define GPP_D1 100 +#define GPP_D2 101 +#define GPP_D3 102 +#define GPP_D4 103 +#define GPP_D5 104 +#define GPP_D6 105 +#define GPP_D7 106 +#define GPP_D8 107 +#define GPP_D9 108 +#define GPP_D10 109 +#define GPP_D11 110 +#define GPP_D12 111 +#define GPP_D13 112 +#define GPP_D14 113 +#define GPP_D15 114 +#define GPP_D16 115 +#define GPP_D17 116 +#define GPP_D18 117 +#define GPP_D19 118 +#define GPP_GSPI2_CLK_LOOPBK 119 + +/* Group U */ +#define GPP_U0 120 +#define GPP_U1 121 +#define GPP_U2 122 +#define GPP_U3 123 +#define GPP_U4 124 +#define GPP_U5 125 +#define GPP_U6 126 +#define GPP_U7 127 +#define GPP_U8 128 +#define GPP_U9 129 +#define GPP_U10 130 +#define GPP_U11 131 +#define GPP_U12 132 +#define GPP_U13 133 +#define GPP_U14 134 +#define GPP_U15 135 +#define GPP_U16 136 +#define GPP_U17 137 +#define GPP_U18 138 +#define GPP_U19 139 +#define GPP_GSPI3_CLK_LOOPBK 140 +#define GPP_GSPI4_CLK_LOOPBK 141 +#define GPP_GSPI5_CLK_LOOPBK 142 +#define GPP_GSPI6_CLK_LOOPBK 143 + +/* Group VGPIO */ +#define CNV_BTEN 144 +#define CNV_BT_HOST_WAKEB 145 +#define CNV_BT_IF_SELECT 146 +#define vCNV_BT_UART_TXD 147 +#define vCNV_BT_UART_RXD 148 +#define vCNV_BT_UART_CTS_B 149 +#define vCNV_BT_UART_RTS_B 150 +#define vCNV_MFUART1_TXD 151 +#define vCNV_MFUART1_RXD 152 +#define vCNV_MFUART1_CTS_B 153 +#define vCNV_MFUART1_RTS_B 154 +#define vUART0_TXD 155 +#define vUART0_RXD 156 +#define vUART0_CTS_B 157 +#define vUART0_RTS_B 158 +#define vISH_UART0_TXD 159 +#define vISH_UART0_RXD 160 +#define vISH_UART0_CTS_B 161 +#define vISH_UART0_RTS_B 162 +#define vCNV_BT_I2S_BCLK 163 +#define vCNV_BT_I2S_WS_SYNC 164 +#define vCNV_BT_I2S_SDO 165 +#define vCNV_BT_I2S_SDI 166 +#define vI2S2_SCLK 167 +#define vI2S2_SFRM 168 +#define vI2S2_TXD 169 +#define vI2S2_RXD 170 + +#define GPIO_COM1_START GPP_S0 +#define GPIO_COM1_END vI2S2_RXD +#define NUM_GPIO_COM1_PADS (vI2S2_RXD - GPP_S0 + 1) + +/* Group GPD */ +#define GPD0 171 +#define GPD1 172 +#define GPD2 173 +#define GPD3 174 +#define GPD4 175 +#define GPD5 176 +#define GPD6 177 +#define GPD7 178 +#define GPD8 179 +#define GPD9 180 +#define GPD10 181 +#define GPD11 182 +#define GPD_INPUT3VSEL 183 +#define GPD_SLP_LANB 184 +#define GPD__SLP_SUSB 185 +#define GPD_WAKEB 186 +#define GPD_DRAM_RESETB 187 + +#define GPIO_COM2_START GPD0 +#define GPIO_COM2_END GPD_DRAM_RESETB +#define NUM_GPIO_COM2_PADS (GPD_DRAM_RESETB - GPD0 + 1) + +/* Group C */ +#define GPP_C0 188 +#define GPP_C1 189 +#define GPP_C2 190 +#define GPP_C3 191 +#define GPP_C4 192 +#define GPP_C5 193 +#define GPP_C6 194 +#define GPP_C7 195 +#define GPP_C8 196 +#define GPP_C9 197 +#define GPP_C10 198 +#define GPP_C11 199 +#define GPP_C12 200 +#define GPP_C13 201 +#define GPP_C14 202 +#define GPP_C15 203 +#define GPP_C16 204 +#define GPP_C17 205 +#define GPP_C18 206 +#define GPP_C19 207 +#define GPP_C20 208 +#define GPP_C21 209 +#define GPP_C22 210 +#define GPP_C23 211 + +/* Group F */ +#define GPP_F0 212 +#define GPP_F1 213 +#define GPP_F2 214 +#define GPP_F3 215 +#define GPP_F4 216 +#define GPP_F5 217 +#define GPP_F6 218 +#define GPP_F7 219 +#define GPP_F8 220 +#define GPP_F9 221 +#define GPP_F10 222 +#define GPP_F11 223 +#define GPP_F12 224 +#define GPP_F13 225 +#define GPP_F14 226 +#define GPP_F15 227 +#define GPP_F16 228 +#define GPP_F17 229 +#define GPP_F18 230 +#define GPP_F19 231 +#define GPP_F20 232 +#define GPP_F21 233 +#define GPP_F22 234 +#define GPP_F23 235 +#define GPP_F_CLK_LOOPBK 236 + +/* Group HVCMOS */ +#define GPP_L_BKLTEN 237 +#define GPP_L_BKLTCTL 238 +#define GPP_L_VDDEN 239 +#define GPP_SYS_PWROK 240 +#define GPP_SYS_RESETB 241 +#define GPP_MLK_RSTB 242 + +/* Group E */ +#define GPP_E0 243 +#define GPP_E1 244 +#define GPP_E2 245 +#define GPP_E3 246 +#define GPP_E4 247 +#define GPP_E5 248 +#define GPP_E6 249 +#define GPP_E7 250 +#define GPP_E8 251 +#define GPP_E9 252 +#define GPP_E10 253 +#define GPP_E11 254 +#define GPP_E12 255 +#define GPP_E13 256 +#define GPP_E14 257 +#define GPP_E15 258 +#define GPP_E16 259 +#define GPP_E17 260 +#define GPP_E18 261 +#define GPP_E19 262 +#define GPP_E20 263 +#define GPP_E21 264 +#define GPP_E22 265 +#define GPP_E23 266 +#define GPP_E_CLK_LOOPBK 267 + +/* Group JTAG */ +#define GPP_JTAG_TDO 268 +#define GPP_JTAG_X 269 +#define GPP_JTAG_PRDYB 270 +#define GPP_JTAG_PREQB 271 +#define GPP_CPU_TRSTB 272 +#define GPP_JTAG_TDI 273 +#define GPP_JTAG_TMS 274 +#define GPP_JTAG_TCK 275 +#define GPP_DBG_PMODE 276 + +#define GPIO_COM4_START GPP_C0 +#define GPIO_COM4_END GPP_DBG_PMODE +#define NUM_GPIO_COM4_PADS (GPP_DBG_PMODE - GPP_C0 + 1) + +/* Group R */ +#define GPP_R0 277 +#define GPP_R1 278 +#define GPP_R2 279 +#define GPP_R3 280 +#define GPP_R4 281 +#define GPP_R5 282 +#define GPP_R6 283 +#define GPP_R7 284 + +/* Group SPI */ +#define GPP_SPI_IO_2 285 +#define GPP_SPI_IO_3 286 +#define GPP_SPI_MOSI_IO_0 287 +#define GPP_SPI_MOSI_IO_1 288 +#define GPP_SPI_TPM_CSB 289 +#define GPP_SPI_FLASH_0_CSB 290 +#define GPP_SPI_FLASH_1_CSB 291 +#define GPP_SPI_CLK 292 +#define GPP_CLK_LOOPBK 293 + +#define GPIO_COM5_START GPP_R0 +#define GPIO_COM5_END GPP_CLK_LOOPBK +#define NUM_GPIO_COM5_PADS (GPP_CLK_LOOPBK - GPP_R0 + 1) + +#define TOTAL_GPIO_COMM (COMM_5 + 1) +#define TOTAL_PADS 294 + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/iomap.h b/src/soc/intel/jasperlake/include/soc/iomap.h new file mode 100644 index 0000000000..5eda08a132 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/iomap.h @@ -0,0 +1,131 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Firmware Architecture Specification + * Document number: 608531 + * Chapter number: 4 + */ + +#ifndef _SOC_TIGERLAKE_IOMAP_H_ +#define _SOC_TIGERLAKE_IOMAP_H_ + +/* + * Memory-mapped I/O registers. + */ +#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS +#define MCFG_BASE_SIZE 0x4000000 + +#define PCH_PRESERVED_BASE_ADDRESS 0xfc800000 +#define PCH_PRESERVED_BASE_SIZE 0x02000000 + +#define PCH_TRACE_HUB_BASE_ADDRESS 0xfc800000 +#define PCH_TRACE_HUB_BASE_SIZE 0x00800000 + +#define UART_BASE_SIZE 0x1000 + +#define UART_BASE_0_ADDRESS 0xfe03e000 +/* Both UART BAR 0 and 1 are 4KB in size */ +#define UART_BASE_0_ADDR(x) (UART_BASE_0_ADDRESS + (2 * \ + UART_BASE_SIZE * (x))) +#define UART_BASE(x) UART_BASE_0_ADDR(x) + +#define DMI_BASE_ADDRESS 0xfeda0000 +#define DMI_BASE_SIZE 0x1000 + +#define EP_BASE_ADDRESS 0xfeda1000 +#define EP_BASE_SIZE 0x1000 + +#define EDRAM_BASE_ADDRESS 0xfed80000 +#define EDRAM_BASE_SIZE 0x4000 + +#define TBT0_BASE_ADDRESS 0xfed84000 +#define TBT0_BASE_SIZE 0x1000 + +#define TBT1_BASE_ADDRESS 0xfed85000 +#define TBT1_BASE_SIZE 0x1000 + +#define TBT2_BASE_ADDRESS 0xfed86000 +#define TBT2_BASE_SIZE 0x1000 + +#define TBT3_BASE_ADDRESS 0xfed87000 +#define TBT3_BASE_SIZE 0x1000 + +#define GFXVT_BASE_ADDRESS 0xfed90000 +#define GFXVT_BASE_SIZE 0x1000 + +#define IPUVT_BASE_ADDRESS 0xfed92000 +#define IPUVT_BASE_SIZE 0x1000 + +#define VTVC0_BASE_ADDRESS 0xfed91000 +#define VTVC0_BASE_SIZE 0x1000 + +#define REG_BASE_ADDRESS 0xfb000000 +#define REG_BASE_SIZE 0x1000 + +#define HPET_BASE_ADDRESS 0xfed00000 + +#define PCH_PWRM_BASE_ADDRESS 0xfe000000 +#define PCH_PWRM_BASE_SIZE 0x10000 + +#define SPI_BASE_ADDRESS 0xfe010000 + +#define GPIO_BASE_SIZE 0x10000 + +#define HECI1_BASE_ADDRESS 0xfeda2000 + +#define VTD_BASE_ADDRESS 0xfed90000 +#define VTD_BASE_SIZE 0x00004000 + +#define ABOVE_4GB_MEM_BASE_ADDRESS (256ULL * GiB) +#define ABOVE_4GB_MEM_BASE_SIZE (256ULL * GiB) + +#if CONFIG(SOC_INTEL_TIGERLAKE_COPY) + +#define MCH_BASE_ADDRESS 0xfedc0000 +#define MCH_BASE_SIZE 0x20000 + +#define EARLY_GSPI_BASE_ADDRESS 0xfe030000 + +#define EARLY_I2C_BASE_ADDRESS 0xfe020000 +#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x2000 * (x))) + +#else /* CONFIG_SOC_INTEL_JASPERLAKE_COPY */ + +#define MCH_BASE_ADDRESS 0xfea80000 +#define MCH_BASE_SIZE 0x8000 + +#define EARLY_GSPI_BASE_ADDRESS 0xfe011000 + +#define EARLY_I2C_BASE_ADDRESS 0xfe040000 +#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x))) + +#endif + +/* + * I/O port address space + */ +#define SMBUS_BASE_ADDRESS 0x0efa0 +#define SMBUS_BASE_SIZE 0x20 + +#define ACPI_BASE_ADDRESS 0x1800 +#define ACPI_BASE_SIZE 0x100 + +#define TCO_BASE_ADDRESS 0x400 +#define TCO_BASE_SIZE 0x20 + +#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS +#define P2SB_SIZE (16 * MiB) + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/irq.h b/src/soc/intel/jasperlake/include/soc/irq.h new file mode 100644 index 0000000000..6ca2588a0d --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/irq.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_IRQ_H_ +#define _SOC_IRQ_H_ + +#if CONFIG(SOC_INTEL_TIGERLAKE_COPY) + #include "irq_tgl.h" +#else + #include "irq_jsl.h" +#endif /* CONFIG_SOC_INTEL_TIGERLAKE_COPY */ + +#endif /* _SOC_IRQ_H_ */ diff --git a/src/soc/intel/jasperlake/include/soc/irq_jsl.h b/src/soc/intel/jasperlake/include/soc/irq_jsl.h new file mode 100644 index 0000000000..a6edd23d97 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/irq_jsl.h @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_JSL_IRQ_H_ +#define _SOC_JSL_IRQ_H_ + +#define GPIO_IRQ14 14 +#define GPIO_IRQ15 15 + +#define PCH_IRQ10 10 +#define PCH_IRQ11 11 + +/* LPSS Devices */ +#define LPSS_I2C0_IRQ 16 +#define LPSS_I2C1_IRQ 17 +#define LPSS_I2C2_IRQ 18 +#define LPSS_I2C3_IRQ 19 +#define LPSS_I2C4_IRQ 32 +#define LPSS_I2C5_IRQ 33 +#define LPSS_SPI0_IRQ 22 +#define LPSS_SPI1_IRQ 23 +#define LPSS_SPI2_IRQ 24 +#define LPSS_UART0_IRQ 20 +#define LPSS_UART1_IRQ 21 +#define LPSS_UART2_IRQ 34 + +/* PCI D:31 F:x */ +#define cAVS_INTA_IRQ 16 +#define SMBUS_INTA_IRQ 16 +#define SMBUS_INTB_IRQ 17 +#define GbE_INTA_IRQ 16 +#define GbE_INTC_IRQ 18 +#define TRACE_HUB_INTA_IRQ 16 +#define TRACE_HUB_INTD_IRQ 19 + +/* PCI D:28 F:x */ +#define PCIE_1_IRQ 16 +#define PCIE_2_IRQ 17 +#define PCIE_3_IRQ 18 +#define PCIE_4_IRQ 19 +#define PCIE_5_IRQ 16 +#define PCIE_6_IRQ 17 +#define PCIE_7_IRQ 18 +#define PCIE_8_IRQ 19 + +/* PCI D:26 F:x */ +#define eMMC_IRQ 16 + +/* PCI D:23 F:x */ +#define SATA_IRQ 16 + +/* PCI D:22 F:x */ +#define HECI_1_IRQ 16 +#define HECI_2_IRQ 17 +#define HECI_3_IRQ 16 +#define HECI_4_IRQ 19 +#define IDER_IRQ 18 +#define KT_IRQ 19 + +/* PCI D:20 F:x */ +#define XHCI_IRQ 16 +#define OTG_IRQ 17 +#define CNViWIFI_IRQ 16 +#define SD_IRQ 19 +#define PMC_SRAM_IRQ 18 + +/* PCI D:18 F:x */ +#define UFS_IRQ 16 + +#define IGFX_IRQ 16 +#define SA_THERMAL_IRQ 16 +#define IPU_IRQ 16 +#define GNA_IRQ 16 + +#endif /* _JSL_IRQ_H_ */ diff --git a/src/soc/intel/jasperlake/include/soc/irq_tgl.h b/src/soc/intel/jasperlake/include/soc/irq_tgl.h new file mode 100644 index 0000000000..6f268c1eae --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/irq_tgl.h @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TGL_IRQ_H_ +#define _SOC_TGL_IRQ_H_ + +#define GPIO_IRQ14 14 +#define GPIO_IRQ15 15 + +#define PCH_IRQ10 10 +#define PCH_IRQ11 11 + +#define LPSS_I2C0_IRQ 27 +#define LPSS_I2C1_IRQ 28 +#define LPSS_I2C2_IRQ 29 +#define LPSS_I2C3_IRQ 30 +#define LPSS_I2C4_IRQ 31 +#define LPSS_I2C5_IRQ 32 +#define LPSS_SPI0_IRQ 36 +#define LPSS_SPI1_IRQ 37 +#define LPSS_SPI2_IRQ 18 +#define LPSS_SPI3_IRQ 23 +#define LPSS_UART0_IRQ 34 +#define LPSS_UART1_IRQ 35 +#define LPSS_UART2_IRQ 33 + +#define HDA_IRQ 16 +#define SMBUS_IRQ 16 +#define TRACEHUB_IRQ 16 + +#define PCIE_1_IRQ 16 +#define PCIE_2_IRQ 17 +#define PCIE_3_IRQ 18 +#define PCIE_4_IRQ 19 +#define PCIE_5_IRQ 16 +#define PCIE_6_IRQ 17 +#define PCIE_7_IRQ 18 +#define PCIE_8_IRQ 19 +#define PCIE_9_IRQ 16 +#define PCIE_10_IRQ 17 +#define PCIE_11_IRQ 18 +#define PCIE_12_IRQ 19 + +#define SATA_IRQ 16 + +#define xHCI_IRQ 16 +#define xDCI_IRQ 17 +#define CNVI_WIFI_IRQ 16 + +#define CNVI_BT_IRQ 18 + +#define THC0_IRQ 16 +#define THC1_IRQ 17 + +#define ISH_IRQ 16 + +#define TBT_PCIe0_IRQ 16 +#define TBT_PCIe1_IRQ 17 +#define TBT_PCIe2_IRQ 18 +#define TBT_PCIe3_IRQ 19 + +#define HECI_1_IRQ 16 +#define HECI_2_IRQ 17 +#define HECI_3_IRQ 16 +#define HECI_4_IRQ 19 + +#define PEG_IRQ 16 +#define IGFX_IRQ 16 +#define THERMAL_IRQ 16 +#define IPU_IRQ 16 +#define GNA_IRQ 16 +#endif /* _TGL_IRQ_H_ */ diff --git a/src/soc/intel/jasperlake/include/soc/itss.h b/src/soc/intel/jasperlake/include/soc/itss.h new file mode 100644 index 0000000000..39794ead73 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/itss.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_TGL_ITSS_H +#define SOC_INTEL_TGL_ITSS_H + +#define GPIO_IRQ_START 50 +#define GPIO_IRQ_END ITSS_MAX_IRQ + +#define ITSS_MAX_IRQ 119 +#define IRQS_PER_IPC 32 +#define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC) + +#endif /* SOC_INTEL_TGL_ITSS_H */ diff --git a/src/soc/intel/jasperlake/include/soc/me.h b/src/soc/intel/jasperlake/include/soc/me.h new file mode 100644 index 0000000000..94331b4c9e --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/me.h @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _TIGERLAKE_ME_H_ +#define _TIGERLAKE_ME_H_ + +/* ME Host Firmware Status register 1 */ +union me_hfsts1 { + u32 data; + struct { + u32 working_state: 4; + u32 spi_protection_mode: 1; + u32 fpt_bad: 1; + u32 operation_state: 3; + u32 fw_init_complete: 1; + u32 ft_bup_ld_flr: 1; + u32 update_in_progress: 1; + u32 error_code: 4; + u32 operation_mode: 4; + u32 reset_count: 4; + u32 boot_options_present: 1; + u32 invoke_enhance_dbg_mode: 1; + u32 bist_test_state: 1; + u32 bist_reset_request: 1; + u32 current_power_source: 2; + u32 reserved: 1; + u32 d0i3_support_valid: 1; + } __packed fields; +}; + +/* ME Host Firmware Status Register 3 */ +union me_hfsts3 { + u32 data; + struct { + u32 reserved_0: 4; + u32 fw_sku: 3; + u32 reserved_7: 2; + u32 reserved_9: 2; + u32 resered_11: 3; + u32 resered_14: 16; + u32 reserved_30: 2; + } __packed fields; +}; +#endif /* _TIGERLAKE_ME_H_ */ diff --git a/src/soc/intel/jasperlake/include/soc/meminit_jsl.h b/src/soc/intel/jasperlake/include/soc/meminit_jsl.h new file mode 100644 index 0000000000..421e31d8e4 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/meminit_jsl.h @@ -0,0 +1,124 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_JASPERLAKE_MEMCFG_INIT_H_ +#define _SOC_JASPERLAKE_MEMCFG_INIT_H_ + +#include <types.h> +#include <fsp/soc_binding.h> + +/* Number of dq bits controlled per dqs */ +#define DQ_BITS_PER_DQS 8 + +/* Number of memory packages, where a "package" represents a 64-bit solution */ +#define DDR_NUM_PACKAGES 2 + +/* Number of DQ byte mappings */ +#define DDR_NUM_BYTE_MAPPINGS 6 + +/* Number of memory DIMM slots available on Jasper Lake */ +#define NUM_DIMM_SLOT 4 + +/* 64-bit Channel identification */ +enum { + DDR_CH0, + DDR_CH1, + DDR_NUM_CHANNELS +}; + +struct spd_by_pointer { + size_t spd_data_len; + uintptr_t spd_data_ptr; +}; + +enum mem_info_read_type { + READ_SPD_CBFS, /* Find SPD file in CBFS. */ + READ_SMBUS, /* Read on-module SPD by SMBUS. */ + READ_SPD_MEMPTR /* Find SPD data from pointer. */ +}; + +struct spd_info { + enum mem_info_read_type read_type; + union spd_data_by { + /* To read on-module SPD when read_type is READ_SMBUS. */ + uint8_t spd_smbus_address[NUM_DIMM_SLOT]; + + /* To identify SPD file when read_type is READ_SPD_CBFS. */ + int spd_index; + + /* To find SPD data when read_type is READ_SPD_MEMPTR. */ + struct spd_by_pointer spd_data_ptr_info; + } spd_spec; +}; + +/* Board-specific memory dq mapping information */ +struct mb_cfg { + + /* + * For each channel, there are 6 sets of DQ byte mappings, + * where each set has a package 0 and a package 1 value (package 0 + * represents the first 64-bit lpddr4 chip combination, and package 1 + * represents the second 64-bit lpddr4 chip combination). + * The first three sets are for CLK, CMD, and CTL. + * The fsp package actually expects 6 sets, even though the last 3 sets + * are not used in JSL. + * We let the meminit_dq_dqs_map routine take care of clearing the + * unused fields for the caller. + * Note that dq_map is only used by LPDDR; it does not need to be + * initialized for designs using DDR4. + */ + uint8_t dq_map[DDR_NUM_CHANNELS][DDR_NUM_BYTE_MAPPINGS][DDR_NUM_PACKAGES]; + + /* + * DQS CPU<>DRAM map Ch0 and Ch1. Each array entry represents a + * mapping of a dq bit on the CPU to the bit it's connected to on + * the memory part. The array index represents the dqs bit number + * on the memory part, and the values in the array represent which + * pin on the CPU that DRAM pin connects to. + * dqs_map is only used by LPDDR; same comments apply as for dq_map + * above. + */ + uint8_t dqs_map[DDR_NUM_CHANNELS][DQ_BITS_PER_DQS]; + + /* + * Rcomp resistor values. These values represent the resistance in + * ohms of the three rcomp resistors attached to the DDR_COMP_0, + * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM. + */ + uint16_t rcomp_resistor[3]; + + /* + * Rcomp target values. These will typically be the following + * values for Jasper Lake : { 80, 40, 40, 40, 30 } + */ + uint16_t rcomp_targets[5]; + + /* + * Early Command Training Enable/Disable Control + * 1 = enable, 0 = disable + */ + uint8_t ect; + + /* Board type */ + uint8_t UserBd; +}; + +/* + * Initialize default memory configurations for Jasper Lake. + */ + +void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg, + const struct spd_info *spd_info, bool half_populated); + +#endif /* _SOC_JASPERLAKE_MEMCFG_INIT_H_ */ diff --git a/src/soc/intel/jasperlake/include/soc/meminit_tgl.h b/src/soc/intel/jasperlake/include/soc/meminit_tgl.h new file mode 100644 index 0000000000..5573fb7110 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/meminit_tgl.h @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef _SOC_MEMINIT_TGL_H_ +#define _SOC_MEMINIT_TGL_H_ + +#include <stddef.h> +#include <stdint.h> +#include <fsp/soc_binding.h> + +#define BYTES_PER_CHANNEL 2 +#define BITS_PER_BYTE 8 +#define DQS_PER_CHANNEL 2 +#define NUM_CHANNELS 8 + +struct spd_by_pointer { + size_t spd_data_len; + uintptr_t spd_data_ptr; +}; + +enum mem_info_read_type { + NOT_EXISTING, /* No memory in this channel */ + READ_SPD_CBFS, /* Find spd file in CBFS. */ + READ_SPD_MEMPTR /* Find spd data from pointer. */ +}; + +struct spd_info { + enum mem_info_read_type read_type; + union spd_data_by { + /* To identify spd file when read_type is READ_SPD_CBFS. */ + int spd_index; + + /* To find spd data when read_type is READ_SPD_MEMPTR. */ + struct spd_by_pointer spd_data_ptr_info; + } spd_spec; +}; + +/* Board-specific memory configuration information */ +struct mb_lpddr4x_cfg { + /* DQ mapping */ + uint8_t dq_map[NUM_CHANNELS][BYTES_PER_CHANNEL * BITS_PER_BYTE]; + + /* + * DQS CPU<>DRAM map. Each array entry represents a + * mapping of a dq bit on the CPU to the bit it's connected to on + * the memory part. The array index represents the dqs bit number + * on the memory part, and the values in the array represent which + * pin on the CPU that DRAM pin connects to. + */ + uint8_t dqs_map[NUM_CHANNELS][DQS_PER_CHANNEL]; + + /* + * Early Command Training Enable/Disable Control + * 1 = enable, 0 = disable + */ + uint8_t ect; +}; + +/* Initialize default memory configurations for dimm0-only lpddr4x */ +void meminit_lpddr4x_dimm0(FSP_M_CONFIG *mem_cfg, + const struct mb_lpddr4x_cfg *board_cfg, + const struct spd_info *spd, + bool half_populated); + +#endif /* _SOC_MEMINIT_TGL_H_ */ diff --git a/src/soc/intel/jasperlake/include/soc/msr.h b/src/soc/intel/jasperlake/include/soc/msr.h new file mode 100644 index 0000000000..7925ea76b0 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/msr.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_MSR_H_ +#define _SOC_MSR_H_ + +#include <intelblocks/msr.h> + +#define MSR_PIC_MSG_CONTROL 0x2e +#define MSR_VR_MISC_CONFIG2 0x636 + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/nvs.h b/src/soc/intel/jasperlake/include/soc/nvs.h new file mode 100644 index 0000000000..cfb189d381 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/nvs.h @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_NVS_H_ +#define _SOC_NVS_H_ + +#include <intelblocks/nvs.h> + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/p2sb.h b/src/soc/intel/jasperlake/include/soc/p2sb.h new file mode 100644 index 0000000000..d483ee399b --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/p2sb.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 3 + */ + +#ifndef _SOC_TIGERLAKE_P2SB_H_ +#define _SOC_TIGERLAKE_P2SB_H_ + +#define HPTC_OFFSET 0x60 +#define HPTC_ADDR_ENABLE_BIT (1 << 7) + +#define PCH_P2SB_EPMASK0 0x220 + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/pch.h b/src/soc/intel/jasperlake/include/soc/pch.h new file mode 100644 index 0000000000..c2f497c1c8 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/pch.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TIGERLAKE_PCH_H_ +#define _SOC_TIGERLAKE_PCH_H_ + +#include <stdint.h> + +#define PCH_TGP 1 +#define PCH_JSP 2 +#define PCH_UNKNOWN_SERIES 0xFF + +#define PCIE_CLK_NOTUSED 0xFF +#define PCIE_CLK_LAN 0x70 +#define PCIE_CLK_FREE 0x80 + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/pci_devs.h b/src/soc/intel/jasperlake/include/soc/pci_devs.h new file mode 100644 index 0000000000..e729864817 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/pci_devs.h @@ -0,0 +1,209 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TIGERLAKE_PCI_DEVS_H_ +#define _SOC_TIGERLAKE_PCI_DEVS_H_ + +#include <device/pci_def.h> + +#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) + +#if !defined(__SIMPLE_DEVICE__) +#include <device/device.h> +#define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) +#else +#define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) +#endif + +/* System Agent Devices */ + +#define SA_DEV_SLOT_ROOT 0x00 +#define SA_DEVFN_ROOT PCI_DEVFN(SA_DEV_SLOT_ROOT, 0) +#if defined(__SIMPLE_DEVICE__) +#define SA_DEV_ROOT PCI_DEV(0, SA_DEV_SLOT_ROOT, 0) +#endif + +#define SA_DEV_SLOT_IGD 0x02 +#define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) +#define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0) + +#define SA_DEV_SLOT_DPTF 0x04 +#define SA_DEVFN_DPTF PCI_DEVFN(SA_DEV_SLOT_DPTF, 0) +#define SA_DEV_DPTF PCI_DEV(0, SA_DEV_SLOT_DPTF, 0) + +#define SA_DEV_SLOT_TBT 0x07 +#define SA_DEVFN_TBT0 PCI_DEVFN(SA_DEV_SLOT_TBT, 0) +#define SA_DEVFN_TBT1 PCI_DEVFN(SA_DEV_SLOT_TBT, 1) +#define SA_DEVFN_TBT2 PCI_DEVFN(SA_DEV_SLOT_TBT, 2) +#define SA_DEVFN_TBT3 PCI_DEVFN(SA_DEV_SLOT_TBT, 3) +#define SA_DEV_TBT0 PCI_DEV(0, SA_DEV_SLOT_TBT, 0) +#define SA_DEV_TBT1 PCI_DEV(0, SA_DEV_SLOT_TBT, 1) +#define SA_DEV_TBT2 PCI_DEV(0, SA_DEV_SLOT_TBT, 2) +#define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3) + +#define SA_DEV_SLOT_IPU 0x05 +#define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) +#define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0) + +/* PCH Devices */ +#define PCH_DEV_SLOT_SIO0 0x10 +#define PCH_DEVFN_CNVI_BT _PCH_DEVFN(SIO0, 2) +#define PCH_DEVFN_THC0 _PCH_DEVFN(SIO0, 6) +#define PCH_DEVFN_THC1 _PCH_DEVFN(SIO0, 7) +#define PCH_DEV_CNVI_BT _PCH_DEV(SIO0, 2) +#define PCH_DEV_THC0 _PCH_DEV(SIO0, 6) +#define PCH_DEV_THC1 _PCH_DEV(SIO0, 7) + +#define PCH_DEV_SLOT_SIO1 0x11 +#define PCH_DEVFN_UART3 _PCH_DEVFN(SIO1, 0) +#define PCH_DEV_UART3 _PCH_DEV(SIO1, 0) + +#define PCH_DEV_SLOT_ISH 0x12 +#define PCH_DEVFN_ISH _PCH_DEVFN(ISH, 0) +#define PCH_DEVFN_GSPI2 _PCH_DEVFN(ISH, 6) +#define PCH_DEV_ISH _PCH_DEV(ISH, 0) +#define PCH_DEV_GSPI2 _PCH_DEV(ISH, 6) + +#define PCH_DEV_SLOT_SIO2 0x13 +#define PCH_DEVFN_GSPI3 _PCH_DEVFN(SIO2, 0) +#define PCH_DEV_GSPI3 _PCH_DEV(SIO2, 0) + +#define PCH_DEV_SLOT_XHCI 0x14 +#define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0) +#define PCH_DEVFN_USBOTG _PCH_DEVFN(XHCI, 1) +#define PCH_DEVFN_SRAM _PCH_DEVFN(XHCI, 2) +#define PCH_DEVFN_CNVI_WIFI _PCH_DEVFN(XHCI, 3) +#define PCH_DEV_XHCI _PCH_DEV(XHCI, 0) +#define PCH_DEV_USBOTG _PCH_DEV(XHCI, 1) +#define PCH_DEV_SRAM _PCH_DEV(XHCI, 2) +#define PCH_DEV_CNVI_WIFI _PCH_DEV(XHCI, 3) + +#if CONFIG(SOC_INTEL_JASPERLAKE_COPY) +#define PCH_DEVFN_SDCARD _PCH_DEVFN(XHCI, 5) +#define PCH_DEV_SDCARD _PCH_DEV(XHCI, 5) +#endif + +#define PCH_DEV_SLOT_SIO3 0x15 +#define PCH_DEVFN_I2C0 _PCH_DEVFN(SIO3, 0) +#define PCH_DEVFN_I2C1 _PCH_DEVFN(SIO3, 1) +#define PCH_DEVFN_I2C2 _PCH_DEVFN(SIO3, 2) +#define PCH_DEVFN_I2C3 _PCH_DEVFN(SIO3, 3) +#define PCH_DEV_I2C0 _PCH_DEV(SIO3, 0) +#define PCH_DEV_I2C1 _PCH_DEV(SIO3, 1) +#define PCH_DEV_I2C2 _PCH_DEV(SIO3, 2) +#define PCH_DEV_I2C3 _PCH_DEV(SIO3, 3) + +#define PCH_DEV_SLOT_CSE 0x16 +#define PCH_DEVFN_CSE _PCH_DEVFN(CSE, 0) +#define PCH_DEVFN_CSE_2 _PCH_DEVFN(CSE, 1) +#define PCH_DEVFN_CSE_IDER _PCH_DEVFN(CSE, 2) +#define PCH_DEVFN_CSE_KT _PCH_DEVFN(CSE, 3) +#define PCH_DEVFN_CSE_3 _PCH_DEVFN(CSE, 4) +#define PCH_DEVFN_CSE_4 _PCH_DEVFN(CSE, 5) +#define PCH_DEV_CSE _PCH_DEV(CSE, 0) +#define PCH_DEV_CSE_2 _PCH_DEV(CSE, 1) +#define PCH_DEV_CSE_IDER _PCH_DEV(CSE, 2) +#define PCH_DEV_CSE_KT _PCH_DEV(CSE, 3) +#define PCH_DEV_CSE_3 _PCH_DEV(CSE, 4) +#define PCH_DEV_CSE_4 _PCH_DEV(CSE, 5) + +#define PCH_DEV_SLOT_SATA 0x17 +#define PCH_DEVFN_SATA _PCH_DEVFN(SATA, 0) +#define PCH_DEV_SATA _PCH_DEV(SATA, 0) + +#define PCH_DEV_SLOT_SIO4 0x19 +#define PCH_DEVFN_I2C4 _PCH_DEVFN(SIO4, 0) +#define PCH_DEVFN_I2C5 _PCH_DEVFN(SIO4, 1) +#define PCH_DEVFN_UART2 _PCH_DEVFN(SIO4, 2) +#define PCH_DEV_I2C4 _PCH_DEV(SIO4, 0) +#define PCH_DEV_I2C5 _PCH_DEV(SIO4, 1) +#define PCH_DEV_UART2 _PCH_DEV(SIO4, 2) + +#if CONFIG(SOC_INTEL_JASPERLAKE_COPY) +#define PCH_DEV_SLOT_STORAGE 0x1a +#define PCH_DEVFN_EMMC _PCH_DEVFN(STORAGE, 0) +#define PCH_DEV_EMMC _PCH_DEV(STORAGE, 0) +#endif + +#define PCH_DEV_SLOT_PCIE 0x1c +#define PCH_DEVFN_PCIE1 _PCH_DEVFN(PCIE, 0) +#define PCH_DEVFN_PCIE2 _PCH_DEVFN(PCIE, 1) +#define PCH_DEVFN_PCIE3 _PCH_DEVFN(PCIE, 2) +#define PCH_DEVFN_PCIE4 _PCH_DEVFN(PCIE, 3) +#define PCH_DEVFN_PCIE5 _PCH_DEVFN(PCIE, 4) +#define PCH_DEVFN_PCIE6 _PCH_DEVFN(PCIE, 5) +#define PCH_DEVFN_PCIE7 _PCH_DEVFN(PCIE, 6) +#define PCH_DEVFN_PCIE8 _PCH_DEVFN(PCIE, 7) +#define PCH_DEV_PCIE1 _PCH_DEV(PCIE, 0) +#define PCH_DEV_PCIE2 _PCH_DEV(PCIE, 1) +#define PCH_DEV_PCIE3 _PCH_DEV(PCIE, 2) +#define PCH_DEV_PCIE4 _PCH_DEV(PCIE, 3) +#define PCH_DEV_PCIE5 _PCH_DEV(PCIE, 4) +#define PCH_DEV_PCIE6 _PCH_DEV(PCIE, 5) +#define PCH_DEV_PCIE7 _PCH_DEV(PCIE, 6) +#define PCH_DEV_PCIE8 _PCH_DEV(PCIE, 7) + +#define PCH_DEV_SLOT_PCIE_1 0x1d +#define PCH_DEVFN_PCIE9 _PCH_DEVFN(PCIE_1, 0) +#define PCH_DEVFN_PCIE10 _PCH_DEVFN(PCIE_1, 1) +#define PCH_DEVFN_PCIE11 _PCH_DEVFN(PCIE_1, 2) +#define PCH_DEVFN_PCIE12 _PCH_DEVFN(PCIE_1, 3) +#define PCH_DEV_PCIE9 _PCH_DEV(PCIE_1, 0) +#define PCH_DEV_PCIE10 _PCH_DEV(PCIE_1, 1) +#define PCH_DEV_PCIE11 _PCH_DEV(PCIE_1, 2) +#define PCH_DEV_PCIE12 _PCH_DEV(PCIE_1, 3) + +#define PCH_DEV_SLOT_SIO5 0x1e +#define PCH_DEVFN_UART0 _PCH_DEVFN(SIO5, 0) +#define PCH_DEVFN_UART1 _PCH_DEVFN(SIO5, 1) +#define PCH_DEVFN_GSPI0 _PCH_DEVFN(SIO5, 2) +#define PCH_DEVFN_GSPI1 _PCH_DEVFN(SIO5, 3) +#define PCH_DEV_UART0 _PCH_DEV(SIO5, 0) +#define PCH_DEV_UART1 _PCH_DEV(SIO5, 1) +#define PCH_DEV_GSPI0 _PCH_DEV(SIO5, 2) +#define PCH_DEV_GSPI1 _PCH_DEV(SIO5, 3) + +#define PCH_DEV_SLOT_ESPI 0x1f +#define PCH_DEV_SLOT_LPC PCH_DEV_SLOT_ESPI +#define PCH_DEVFN_ESPI _PCH_DEVFN(ESPI, 0) +#define PCH_DEVFN_P2SB _PCH_DEVFN(ESPI, 1) +#define PCH_DEVFN_PMC _PCH_DEVFN(ESPI, 2) +#define PCH_DEVFN_HDA _PCH_DEVFN(ESPI, 3) +#define PCH_DEVFN_SMBUS _PCH_DEVFN(ESPI, 4) +#define PCH_DEVFN_SPI _PCH_DEVFN(ESPI, 5) +#define PCH_DEVFN_GBE _PCH_DEVFN(ESPI, 6) +#define PCH_DEVFN_TRACEHUB _PCH_DEVFN(ESPI, 7) +#define PCH_DEV_ESPI _PCH_DEV(ESPI, 0) +#define PCH_DEV_LPC PCH_DEV_ESPI +#define PCH_DEV_P2SB _PCH_DEV(ESPI, 1) + +#if !ENV_RAMSTAGE +/* + * PCH_DEV_PMC is intentionally not defined in RAMSTAGE since PMC device gets + * hidden from PCI bus after call to FSP-S. This leads to resource allocator + * dropping it from the root bus as unused device. All references to PCH_DEV_PMC + * would then return NULL and can go unnoticed if not handled properly. Since, + * this device does not have any special chip config associated with it, it is + * okay to not provide the definition for it in ramstage. + */ +#define PCH_DEV_PMC _PCH_DEV(ESPI, 2) +#endif + +#define PCH_DEV_HDA _PCH_DEV(ESPI, 3) +#define PCH_DEV_SMBUS _PCH_DEV(ESPI, 4) +#define PCH_DEV_SPI _PCH_DEV(ESPI, 5) +#define PCH_DEV_GBE _PCH_DEV(ESPI, 6) +#define PCH_DEV_TRACEHUB _PCH_DEV(ESPI, 7) + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/pcr_ids.h b/src/soc/intel/jasperlake/include/soc/pcr_ids.h new file mode 100644 index 0000000000..4143892f87 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/pcr_ids.h @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 31-35 + */ + +#ifndef SOC_TIGERLAKE_PCR_H +#define SOC_TIGERLAKE_PCR_H +/* + * Port ids + */ +#define PID_EMMC 0x52 +#define PID_SDX 0x53 + +#define PID_GPIOCOM0 0x6e +#define PID_GPIOCOM1 0x6d +#define PID_GPIOCOM2 0x6c +#define PID_GPIOCOM4 0x6a +#define PID_GPIOCOM5 0x69 + +#define PID_DMI 0x88 +#define PID_PSTH 0x89 +#define PID_CSME0 0x90 +#define PID_ISCLK 0xad +#define PID_PSF1 0xba +#define PID_PSF2 0xbb +#define PID_PSF3 0xbc +#define PID_PSF4 0xbd +#define PID_SCS 0xc0 +#define PID_RTC 0xc3 +#define PID_ITSS 0xc4 +#define PID_ESPI 0xc7 +#define PID_SERIALIO 0xcb + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/pm.h b/src/soc/intel/jasperlake/include/soc/pm.h new file mode 100644 index 0000000000..14fa5d0c08 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/pm.h @@ -0,0 +1,182 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 4 + */ + +#ifndef _SOC_PM_H_ +#define _SOC_PM_H_ + +#define PM1_STS 0x00 +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define BM_STS (1 << 4) +#define TMROF_STS (1 << 0) +#define PM1_EN 0x02 +#define PCIEXPWAK_DIS (1 << 14) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) +#define PM1_CNT 0x04 +#define GBL_RLS (1 << 2) +#define BM_RLD (1 << 1) +#define SCI_EN (1 << 0) +#define PM1_TMR 0x08 +#define SMI_EN 0x30 +#define XHCI_SMI_EN (1 << 31) +#define ME_SMI_EN (1 << 30) +#define ESPI_SMI_EN (1 << 28) +#define GPIO_UNLOCK_SMI_EN (1 << 27) +#define INTEL_USB2_EN (1 << 18) +#define LEGACY_USB2_EN (1 << 17) +#define PERIODIC_EN (1 << 14) +#define TCO_SMI_EN (1 << 13) +#define MCSMI_EN (1 << 11) +#define BIOS_RLS (1 << 7) +#define SWSMI_TMR_EN (1 << 6) +#define APMC_EN (1 << 5) +#define SLP_SMI_EN (1 << 4) +#define LEGACY_USB_EN (1 << 3) +#define BIOS_EN (1 << 2) +#define EOS (1 << 1) +#define GBL_SMI_EN (1 << 0) +#define SMI_STS 0x34 +#define SMI_STS_BITS 32 +#define XHCI_SMI_STS_BIT 31 +#define ME_SMI_STS_BIT 30 +#define ESPI_SMI_STS_BIT 28 +#define GPIO_UNLOCK_SMI_STS_BIT 27 +#define SPI_SMI_STS_BIT 26 +#define SCC_SMI_STS_BIT 25 +#define MONITOR_STS_BIT 21 +#define PCI_EXP_SMI_STS_BIT 20 +#define SMBUS_SMI_STS_BIT 16 +#define SERIRQ_SMI_STS_BIT 15 +#define PERIODIC_STS_BIT 14 +#define TCO_STS_BIT 13 +#define DEVMON_STS_BIT 12 +#define MCSMI_STS_BIT 11 +#define GPIO_STS_BIT 10 +#define GPE0_STS_BIT 9 +#define PM1_STS_BIT 8 +#define SWSMI_TMR_STS_BIT 6 +#define APM_STS_BIT 5 +#define SMI_ON_SLP_EN_STS_BIT 4 +#define LEGACY_USB_STS_BIT 3 +#define BIOS_STS_BIT 2 +#define GPE_CNTL 0x42 +#define SWGPE_CTRL (1 << 1) +#define DEVACT_STS 0x44 +#define PM2_CNT 0x50 + +#define GPE0_REG_MAX 4 +#define GPE0_REG_SIZE 32 +#define GPE0_STS(x) (0x60 + ((x) * 4)) +#define GPE_31_0 0 /* 0x60/0x70 = GPE[31:0] */ +#define GPE_63_32 1 /* 0x64/0x74 = GPE[63:32] */ +#define GPE_95_64 2 /* 0x68/0x78 = GPE[95:64] */ +#define GPE_STD 3 /* 0x6c/0x7c = Standard GPE */ +#define GPE_STS_RSVD GPE_STD +#define WADT_STS (1 << 18) +#define GPIO_T2_STS (1 << 15) +#define ESPI_STS (1 << 14) +#define PME_B0_STS (1 << 13) +#define ME_SCI_STS (1 << 12) +#define PME_STS (1 << 11) +#define BATLOW_STS (1 << 10) +#define PCI_EXP_STS (1 << 9) +#define SMB_WAK_STS (1 << 7) +#define TCOSCI_STS (1 << 6) +#define SWGPE_STS (1 << 2) +#define HOT_PLUG_STS (1 << 1) +#define GPE0_EN(x) (0x70 + ((x) * 4)) +#define WADT_EN (1 << 18) +#define GPIO_T2_EN (1 << 15) +#define ESPI_EN (1 << 14) +#define PME_B0_EN_BIT 13 +#define PME_B0_EN (1 << PME_B0_EN_BIT) +#define ME_SCI_EN (1 << 12) +#define PME_EN (1 << 11) +#define BATLOW_EN (1 << 10) +#define PCI_EXP_EN (1 << 9) +#define TCOSCI_EN (1 << 6) +#define SWGPE_EN (1 << 2) +#define HOT_PLUG_EN (1 << 1) + +#define EN_BLOCK 3 + +/* + * Enable SMI generation: + * - on APMC writes (io 0xb2) + * - on writes to SLP_EN (sleep states) + * - on writes to GBL_RLS (bios commands) + * - on eSPI events (does nothing on LPC systems) + * No SMIs: + * - on TCO events, unless enabled in common code + * - on microcontroller writes (io 0x62/0x66) + */ +#define ENABLE_SMI_PARAMS \ + (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS) + +#define PSS_RATIO_STEP 2 +#define PSS_MAX_ENTRIES 8 +#define PSS_LATENCY_TRANSITION 10 +#define PSS_LATENCY_BUSMASTER 10 + +#if !defined(__ACPI__) + +#include <arch/acpi.h> +#include <soc/gpe.h> +#include <soc/iomap.h> +#include <soc/smbus.h> +#include <soc/pmc.h> + +struct chipset_power_state { + uint16_t pm1_sts; + uint16_t pm1_en; + uint32_t pm1_cnt; + uint16_t tco1_sts; + uint16_t tco2_sts; + uint32_t gpe0_sts[4]; + uint32_t gpe0_en[4]; + uint32_t gen_pmcon_a; + uint32_t gen_pmcon_b; + uint32_t gblrst_cause[2]; + uint32_t prev_sleep_state; +} __packed; + +/* Get base address PMC memory mapped registers. */ +uint8_t *pmc_mmio_regs(void); + +/* Get base address of TCO I/O registers. */ +uint16_t smbus_tco_regs(void); + +/* Set the DISB after DRAM init */ +void pmc_set_disb(void); + +/* Clear PMCON status bits */ +void pmc_clear_pmcon_sts(void); + +/* STM Support */ +uint16_t get_pmbase(void); +#endif /* !defined(__ACPI__) */ +#endif diff --git a/src/soc/intel/jasperlake/include/soc/pmc.h b/src/soc/intel/jasperlake/include/soc/pmc.h new file mode 100644 index 0000000000..0ec1d36e44 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/pmc.h @@ -0,0 +1,168 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TIGERLAKE_PMC_H_ +#define _SOC_TIGERLAKE_PMC_H_ + +/* PCI Configuration Space (D31:F2): PMC */ +#define PWRMBASE 0x10 +#define ABASE 0x20 + +/* Memory mapped IO registers in PMC */ +#define GEN_PMCON_A 0x1020 +#define DC_PP_DIS (1 << 30) +#define DSX_PP_DIS (1 << 29) +#define AG3_PP_EN (1 << 28) +#define SX_PP_EN (1 << 27) +#define ALLOW_ICLK_PLL_SD_INC0 (1 << 26) +#define GBL_RST_STS (1 << 24) +#define DISB (1 << 23) +#define ALLOW_OPI_PLL_SD_INC0 (1 << 22) +#define MEM_SR (1 << 21) +#define ALLOW_SPXB_CG_INC0 (1 << 20) +#define ALLOW_L1LOW_C0 (1 << 19) +#define MS4V (1 << 18) +#define ALLOW_L1LOW_OPI_ON (1 << 17) +#define SUS_PWR_FLR (1 << 16) +#define PME_B0_S5_DIS (1 << 15) +#define PWR_FLR (1 << 14) +#define ALLOW_L1LOW_BCLKREQ_ON (1 << 13) +#define DIS_SLP_X_STRCH_SUS_UP (1 << 12) +#define SLP_S3_MIN_ASST_WDTH_MASK (3 << 10) +#define SLP_S3_MIN_ASST_WDTH_60USEC (0 << 10) +#define SLP_S3_MIN_ASST_WDTH_1MS (1 << 10) +#define SLP_S3_MIN_ASST_WDTH_50MS (2 << 10) +#define SLP_S3_MIN_ASST_WDTH_2S (3 << 10) +#define HOST_RST_STS (1 << 9) +#define ESPI_SMI_LOCK (1 << 8) +#define S4MAW_MASK (3 << 4) +#define S4MAW_1S (1 << 4) +#define S4MAW_2S (2 << 4) +#define S4MAW_3S (3 << 4) +#define S4MAW_4S (0 << 4) +#define S4ASE (1 << 3) +#define PER_SMI_SEL_MASK (3 << 1) +#define SMI_RATE_64S (0 << 1) +#define SMI_RATE_32S (1 << 1) +#define SMI_RATE_16S (2 << 1) +#define SMI_RATE_8S (3 << 1) +#define SLEEP_AFTER_POWER_FAIL (1 << 0) + +#define GEN_PMCON_B 0x1024 +#define SLP_STR_POL_LOCK (1 << 18) +#define ACPI_BASE_LOCK (1 << 17) +#define PM_DATA_BAR_DIS (1 << 16) +#define WOL_EN_OVRD (1 << 13) +#define BIOS_PCI_EXP_EN (1 << 10) +#define PWRBTN_LVL (1 << 9) +#define SMI_LOCK (1 << 4) +#define RTC_BATTERY_DEAD (1 << 2) + +#define ETR 0x1048 +#define CF9_LOCK (1 << 31) +#define CF9_GLB_RST (1 << 20) + +#define SSML 0x104C +#define SSML_SSL_DS (0 << 0) +#define SSML_SSL_EN (1 << 0) + +#define SSMC 0x1050 +#define SSMC_SSMS (1 << 0) + +#define SSMD 0x1054 +#define SSMD_SSD_MASK (0xffff << 0) + +#define PRSTS 0x1810 + +#define S3_PWRGATE_POL 0x1828 +#define S3DC_GATE_SUS (1 << 1) +#define S3AC_GATE_SUS (1 << 0) + +#define S4_PWRGATE_POL 0x182c +#define S4DC_GATE_SUS (1 << 1) +#define S4AC_GATE_SUS (1 << 0) + +#define S5_PWRGATE_POL 0x1830 +#define S5DC_GATE_SUS (1 << 15) +#define S5AC_GATE_SUS (1 << 14) + +#define DSX_CFG 0x1834 +#define REQ_CNV_NOWAKE_DSX (1 << 4) +#define REQ_BATLOW_DSX (1 << 3) +#define DSX_EN_WAKE_PIN (1 << 2) +#define DSX_DIS_AC_PRESENT_PD (1 << 1) +#define DSX_EN_LAN_WAKE_PIN (1 << 0) +#define DSX_CFG_MASK (0x1f << 0) + +#define PMSYNC_TPR_CFG 0x18C4 +#define PCH2CPU_TPR_CFG_LOCK (1 << 31) +#define PCH2CPU_TT_EN (1 << 26) + +#define PCH_PWRM_ACPI_TMR_CTL 0x18FC +#define GPIO_GPE_CFG 0x1920 +#define GPE0_DWX_MASK 0xf +#define GPE0_DW_SHIFT(x) (4*(x)) + +#if CONFIG(SOC_INTEL_TIGERLAKE_COPY) + + #define PMC_GPP_B 0x0 + #define PMC_GPP_T 0x1 + #define PMC_GPP_A 0x2 + #define PMC_GPP_R 0x3 + #define PMC_GPD 0x4 + #define PMC_GPP_S 0x5 + #define PMC_GPP_H 0x6 + #define PMC_GPP_D 0x7 + #define PMC_GPP_U 0x8 + #define PMC_GPP_F 0xA + #define PMC_GPP_C 0xB + #define PMC_GPP_E 0xC + +#elif CONFIG(SOC_INTEL_JASPERLAKE_COPY) + + #define PMC_GPP_A 0x0 + #define PMC_GPP_B 0x1 + #define PMC_GPP_F 0x2 + #define PMC_GPD 0x3 + #define PMC_GPP_R 0x4 + #define PMC_GPP_S 0x6 + #define PMC_GPP_D 0x7 + #define PMC_GPP_C 0x8 + #define PMC_GPP_H 0xA + #define PMC_GPP_E 0xF + +#endif + +#define GBLRST_CAUSE0 0x1924 +#define GBLRST_CAUSE0_THERMTRIP (1 << 5) +#define GBLRST_CAUSE1 0x1928 + +#define CPPMVRIC 0x1B1C +#define XTALSDQDIS (1 << 22) + +#define IRQ_REG ACTL +#define SCI_IRQ_ADJUST 0 +#define ACTL 0x1BD8 +#define PWRM_EN (1 << 8) +#define ACPI_EN (1 << 7) +#define SCI_IRQ_SEL (7 << 0) + +#define SCIS_IRQ9 0 +#define SCIS_IRQ10 1 +#define SCIS_IRQ11 2 +#define SCIS_IRQ20 4 +#define SCIS_IRQ21 5 +#define SCIS_IRQ22 6 +#define SCIS_IRQ23 7 +#endif diff --git a/src/soc/intel/jasperlake/include/soc/ramstage.h b/src/soc/intel/jasperlake/include/soc/ramstage.h new file mode 100644 index 0000000000..a8c8fdd7b2 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/ramstage.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_RAMSTAGE_H_ +#define _SOC_RAMSTAGE_H_ + +#include <device/device.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <soc/soc_chip.h> + +void mainboard_silicon_init_params(FSP_S_CONFIG *params); +void soc_init_pre_device(void *chip_info); + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/romstage.h b/src/soc/intel/jasperlake/include/soc/romstage.h new file mode 100644 index 0000000000..1672e8b5ca --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/romstage.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_ROMSTAGE_H_ +#define _SOC_ROMSTAGE_H_ + +#include <fsp/api.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd); +void systemagent_early_init(void); +void pch_init(void); + +/* Board type */ +enum board_type { + BOARD_TYPE_MOBILE = 0, + BOARD_TYPE_DESKTOP = 1, + BOARD_TYPE_ULT_ULX = 5, + BOARD_TYPE_SERVER = 7 +}; + +#endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/jasperlake/include/soc/serialio.h b/src/soc/intel/jasperlake/include/soc/serialio.h new file mode 100644 index 0000000000..509f0b0f14 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/serialio.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SERIALIO_H_ +#define _SERIALIO_H_ + +enum { + PchSerialIoDisabled, + PchSerialIoPci, + PchSerialIoHidden, + PchSerialIoLegacyUart, + PchSerialIoSkipInit +}; + +enum { + PchSerialIoIndexI2C0, + PchSerialIoIndexI2C1, + PchSerialIoIndexI2C2, + PchSerialIoIndexI2C3, + PchSerialIoIndexI2C4, + PchSerialIoIndexI2C5, +}; + +enum { + PchSerialIoIndexGSPI0, + PchSerialIoIndexGSPI1, + PchSerialIoIndexGSPI2, + PchSerialIoIndexGSPI3, +}; + +enum { + PchSerialIoIndexUART0, + PchSerialIoIndexUART1, + PchSerialIoIndexUART2, +}; + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/smbus.h b/src/soc/intel/jasperlake/include/soc/smbus.h new file mode 100644 index 0000000000..3fb8291698 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/smbus.h @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor PCH Datasheet + * Document number: 575857 + * Chapter number: 6 + */ + +#ifndef _SOC_TIGERLAKE_SMBUS_H_ +#define _SOC_TIGERLAKE_SMBUS_H_ + +/* IO and MMIO registers under primary BAR */ + +/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ +#define TCO1_STS 0x04 +#define TCO_TIMEOUT (1 << 3) +#define TCO2_STS 0x06 +#define TCO_STS_SECOND_TO (1 << 1) +#define TCO_INTRD_DET (1 << 0) +#define TCO1_CNT 0x08 +#define TCO_LOCK (1 << 12) +#define TCO_TMR_HLT (1 << 11) +#define TCO2_CNT 0x0A +#define TCO_INTRD_SEL_MASK (3 << 1) +#define TCO_INTRD_SEL_SMI (1 << 2) +#define TCO_INTRD_SEL_INT (1 << 1) + +/* + * Default slave address value for PCH. This value is set to match default + * value set by hardware. It is useful since PCH is able to respond even + * before CPU is up. This is reset by RSMRST# but not by PLTRST#. + */ +#define SMBUS_SLAVE_ADDR 0x44 + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/soc_chip.h b/src/soc/intel/jasperlake/include/soc/soc_chip.h new file mode 100644 index 0000000000..250aa9a0aa --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/soc_chip.h @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TIGERLAKE_SOC_CHIP_H_ +#define _SOC_TIGERLAKE_SOC_CHIP_H_ + +#include "../../chip.h" + +#endif /* _SOC_TIGERLAKE_SOC_CHIP_H_ */ diff --git a/src/soc/intel/jasperlake/include/soc/systemagent.h b/src/soc/intel/jasperlake/include/soc/systemagent.h new file mode 100644 index 0000000000..d8c8ad47da --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/systemagent.h @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor SA Datasheet + * Document number: 571131 + * Chapter number: 3 + */ + +#ifndef SOC_TIGERLAKE_SYSTEMAGENT_H +#define SOC_TIGERLAKE_SYSTEMAGENT_H + +#include <intelblocks/systemagent.h> + +/* Device 0:0.0 PCI configuration space */ + +#define EPBAR 0x40 +#define DMIBAR 0x68 +#define SMRAM 0x88 /* System Management RAM Control */ +#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRAME (1 << 3) +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) +#define CAPID0_A 0xe4 +#define VTD_DISABLE (1 << 23) + +#define BIOS_RESET_CPL 0x5da8 +#define GFXVTBAR 0x5400 +#define EDRAMBAR 0x5408 +#define VTVC0BAR 0x5410 +#define REGBAR 0x5420 +#define IPUVTBAR 0x7880 +#define TBT0BAR 0x7888 +#define TBT1BAR 0x7890 +#define TBT2BAR 0x7898 +#define TBT3BAR 0x78A0 +#define MAX_TBT_PCIE_PORT 4 + +#define VTBAR_ENABLED 0x01 +#define VTBAR_MASK 0x7ffffff000ull + +#define MCH_PKG_POWER_LIMIT_LO 0x59a0 +#define MCH_PKG_POWER_LIMIT_HI 0x59a4 +#define MCH_DDR_POWER_LIMIT_LO 0x58e0 +#define MCH_DDR_POWER_LIMIT_HI 0x58e4 + +#define IMRBASE 0x6A40 +#define IMRLIMIT 0x6A48 + +static const struct sa_mmio_descriptor soc_vtd_resources[] = { + { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" }, + { IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR" }, + { TBT0BAR, TBT0_BASE_ADDRESS, TBT0_BASE_SIZE, "TBT0BAR" }, + { TBT1BAR, TBT1_BASE_ADDRESS, TBT1_BASE_SIZE, "TBT1BAR" }, + { TBT2BAR, TBT2_BASE_ADDRESS, TBT2_BASE_SIZE, "TBT2BAR" }, + { TBT3BAR, TBT3_BASE_ADDRESS, TBT3_BASE_SIZE, "TBT3BAR" }, + { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" }, +}; + +#define V_P2SB_CFG_IBDF_BUS 0 +#define V_P2SB_CFG_IBDF_DEV 30 +#define V_P2SB_CFG_IBDF_FUNC 7 +#define V_P2SB_CFG_HBDF_BUS 0 +#define V_P2SB_CFG_HBDF_DEV 30 +#define V_P2SB_CFG_HBDF_FUNC 6 + +#endif diff --git a/src/soc/intel/jasperlake/include/soc/usb.h b/src/soc/intel/jasperlake/include/soc/usb.h new file mode 100644 index 0000000000..33c0bf0bf9 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/usb.h @@ -0,0 +1,151 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _SOC_USB_H_ +#define _SOC_USB_H_ + +#include <stdint.h> + +/* Per Port HS Transmitter Emphasis */ +#define USB2_EMP_OFF 0 +#define USB2_DE_EMP_ON 1 +#define USB2_PRE_EMP_ON 2 +#define USB2_DE_EMP_ON_PRE_EMP_ON 3 + +/* Per Port Half Bit Pre-emphasis */ +#define USB2_FULL_BIT_PRE_EMP 0 +#define USB2_HALF_BIT_PRE_EMP 1 + +/* Per Port HS Preemphasis Bias */ +#define USB2_BIAS_0MV 0 +#define USB2_BIAS_11P25MV 1 +#define USB2_BIAS_16P9MV 2 +#define USB2_BIAS_28P15MV 3 +#define USB2_BIAS_39P35MV 5 +#define USB2_BIAS_45MV 6 +#define USB2_BIAS_56P3MV 7 + +struct usb2_port_config { + uint8_t enable; + uint8_t ocpin; + uint8_t tx_bias; + uint8_t tx_emp_enable; + uint8_t pre_emp_bias; + uint8_t pre_emp_bit; +}; + +/* USB Overcurrent pins definition */ +enum { + OC0 = 0, + OC1, + OC2, + OC3, + OC4, + OC5, + OC6, + OC7, + OCMAX, + OC_SKIP = 0xff, /* Skip OC programming */ +}; + +/* Standard USB Port based on length: + * - External + * - Back Panel + * - OTG + * - M.2 + * - Internal device down */ + +#define USB2_PORT_EMPTY { \ + .enable = 0, \ + .ocpin = OC_SKIP, \ + .tx_bias = USB2_BIAS_0MV, \ + .tx_emp_enable = USB2_EMP_OFF, \ + .pre_emp_bias = USB2_BIAS_0MV, \ + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ +} + +/* Length = 11.5"-12" */ +#define USB2_PORT_LONG(pin) { \ + .enable = 1, \ + .ocpin = (pin), \ + .tx_bias = USB2_BIAS_39P35MV, \ + .tx_emp_enable = USB2_PRE_EMP_ON, \ + .pre_emp_bias = USB2_BIAS_56P3MV, \ + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ +} + +/* Length = 6"-11.49" */ +#define USB2_PORT_MID(pin) { \ + .enable = 1, \ + .ocpin = (pin), \ + .tx_bias = USB2_BIAS_0MV, \ + .tx_emp_enable = USB2_PRE_EMP_ON, \ + .pre_emp_bias = USB2_BIAS_56P3MV, \ + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ +} + +/* Length = 3"-5.99" */ +#define USB2_PORT_SHORT(pin) { \ + .enable = 1, \ + .ocpin = (pin), \ + .tx_bias = USB2_BIAS_39P35MV, \ + .tx_emp_enable = USB2_PRE_EMP_ON | USB2_DE_EMP_ON, \ + .pre_emp_bias = USB2_BIAS_39P35MV, \ + .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, \ +} + +/* Max TX and Pre-emp settings */ +#define USB2_PORT_MAX(pin) { \ + .enable = 1, \ + .ocpin = (pin), \ + .tx_bias = USB2_BIAS_56P3MV, \ + .tx_emp_enable = USB2_PRE_EMP_ON, \ + .pre_emp_bias = USB2_BIAS_56P3MV, \ + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ +} + +/* Type-C Port, no BC1.2 charge detect module / MUX + * Length = 3.0" - 9.00" */ +#define USB2_PORT_TYPE_C(pin) { \ + .enable = 1, \ + .ocpin = (pin), \ + .tx_bias = USB2_BIAS_0MV, \ + .tx_emp_enable = USB2_PRE_EMP_ON, \ + .pre_emp_bias = USB2_BIAS_56P3MV, \ + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ +} + +struct usb3_port_config { + uint8_t enable; + uint8_t ocpin; + uint8_t tx_de_emp; + uint8_t tx_downscale_amp; +}; + +#define USB3_PORT_EMPTY { \ + .enable = 0, \ + .ocpin = OC_SKIP, \ + .tx_de_emp = 0x00, \ + .tx_downscale_amp = 0x00, \ +} + +#define USB3_PORT_DEFAULT(pin) { \ + .enable = 1, \ + .ocpin = (pin), \ + .tx_de_emp = 0x0, \ + .tx_downscale_amp = 0x00, \ +} + +#endif |