soc/intel/jasperlake: Remove Tiger Lake SoC code from Jasper Lake

This is a follow-up patch to initial copy patch for Jasper Lake SoC.
Remove all Tiger Lake specfic code from Jasper Lake SoC code.

BUG=b:150217037

Change-Id: I44dc6bf55ca18a3f0c350f5c3e9fae2996958648
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39824
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 2 insertions, 2 deletions

diff --git a/src/soc/intel/jasperlake/smihandler.c b/src/soc/intel/jasperlake/smihandler.c
index 67e59a26a0..3f6cfd2d7f 100644
--- a/src/soc/intel/jasperlake/smihandler.c
+++ b/src/soc/intel/jasperlake/smihandler.c
@@ -24,12 +24,12 @@
  * Specific SOC SMI handler during ramstage finalize phase
  *
  * BIOS can't make CSME function disable as is due to POSTBOOT_SAI
- * restriction in place from TGP chipset. Hence create SMI Handler to
+ * restriction in place from JSP chipset. Hence create SMI Handler to
  * perform CSME function disabling logic during SMM mode.
  */
 void smihandler_soc_at_finalize(void)
 {
-	const struct soc_intel_tigerlake_config *config;
+	const struct soc_intel_jasperlake_config *config;
 
 	config = config_of_soc();