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authorAamir Bohra <aamir.bohra@intel.com>2020-03-25 13:20:34 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-03-28 14:08:23 +0000
commit512b77abb582e6c2566d3873b273dd32731e7bae (patch)
tree8807f78791588d361bd1cef00e11f6619203c713 /src/soc/intel/jasperlake/uart.c
parentdd7acaad27e4f99f025df7f06d71dbb49d0e399b (diff)
downloadcoreboot-512b77abb582e6c2566d3873b273dd32731e7bae.tar.xz
soc/intel/jasperlake: Remove Tiger Lake SoC code from Jasper Lake
This is a follow-up patch to initial copy patch for Jasper Lake SoC. Remove all Tiger Lake specfic code from Jasper Lake SoC code. BUG=b:150217037 Change-Id: I44dc6bf55ca18a3f0c350f5c3e9fae2996958648 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39824 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/jasperlake/uart.c')
-rw-r--r--src/soc/intel/jasperlake/uart.c6
1 files changed, 0 insertions, 6 deletions
diff --git a/src/soc/intel/jasperlake/uart.c b/src/soc/intel/jasperlake/uart.c
index 03b4469a98..50849560ac 100644
--- a/src/soc/intel/jasperlake/uart.c
+++ b/src/soc/intel/jasperlake/uart.c
@@ -12,12 +12,6 @@
* GNU General Public License for more details.
*/
-/*
- * This file is created based on Intel Tiger Lake Processor PCH Datasheet
- * Document number: 575857
- * Chapter number: 9
- */
-
#include <console/console.h>
#include <device/pci_def.h>
#include <intelblocks/gpio.h>