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authorJonathan Zhang <jonzhang@fb.com>2020-06-17 16:03:18 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-06-25 11:57:32 +0000
commit01e38559c36e5ca9e1cf69c7a674bf10aa156dd9 (patch)
tree8805140d953fd65ccee600bbc4b418594d2e672b /src/soc/intel/jasperlake
parent951a409f669138bae25e255ec131b5fe0b0daec0 (diff)
downloadcoreboot-01e38559c36e5ca9e1cf69c7a674bf10aa156dd9.tar.xz
drivers/intel/fsp2_0: decouple FSP_PEIM_TO_PEIM_INTERFACE from FSP 2.1
Not all FSPs based on FSP 2.1 supports the feature of external PPI interface pulled in via FSP_PEIM_TO_PEIM_INTERFACE. Deselect FSP_PEIM_TO_PEIM_INTERFACE when PLATFORM_USES_FSP2_1 is selected. Update Kconfig of SOCs affected (icelake, jasperlake, tigerlake). Change-Id: I5df03f8bcf15c9e05c9fd904a79f740260a3aed7 Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel/jasperlake')
-rw-r--r--src/soc/intel/jasperlake/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
index 72b0c5ef9d..89bbdd3614 100644
--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -33,6 +33,7 @@ config CPU_SPECIFIC_OPTIONS
select PARALLEL_MP_AP_WORK
select MICROCODE_BLOB_UNDISCLOSED
select PLATFORM_USES_FSP2_1
+ select FSP_PEIM_TO_PEIM_INTERFACE
select REG_SCRIPT
select SMP
select PMC_GLOBAL_RESET_ENABLE_LOCK