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authorRonak Kanabar <ronak.kanabar@intel.com>2020-07-24 17:47:49 +0530
committerPatrick Georgi <pgeorgi@google.com>2020-08-25 12:59:57 +0000
commit2d5b252fd20493e67795a1af33ef730b1552afa3 (patch)
tree724b2ce0db45e086c708bc1ec57b1d0ff182f68f /src/soc/intel/jasperlake
parent8c4ad359fb5aabc85e6828550dd1fe317bb59da6 (diff)
downloadcoreboot-2d5b252fd20493e67795a1af33ef730b1552afa3.tar.xz
soc/intel/jasperlake: Disable multiphase SI init
Jasper Lake does not have any use case for multiphase SI init so Disable it. BUG=b:162184827 BRANCH=None TEST=Build and boot JSLRVP Cq-Depend: chrome-internal:3221772 Change-Id: I2d591b46c403e68ff0b41ac8f87c742ae774111e Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Diffstat (limited to 'src/soc/intel/jasperlake')
-rw-r--r--src/soc/intel/jasperlake/fsp_params.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c
index c45af27ece..40be0d45bf 100644
--- a/src/soc/intel/jasperlake/fsp_params.c
+++ b/src/soc/intel/jasperlake/fsp_params.c
@@ -349,6 +349,12 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
mainboard_silicon_init_params(params);
}
+/* Disable Multiphase Si init */
+int soc_fsp_multi_phase_init_is_enable(void)
+{
+ return 0;
+}
+
/* Mainboard GPIO Configuration */
__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
{