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| author | Subrata Banik <subrata.banik@intel.com> | 2020-09-29 14:36:40 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-10-03 04:19:00 +0000 |
| commit | 8971ccd576a7b0edbd02101b0c3bc3541cb6a741 (patch) | |
| tree | 6b1d3ac94497ad7a35428cccd8504342bef7b94f /src/soc/intel/jasperlake | |
| parent | 78463a7d26506d6e38917e9bf98ac0dd82663565 (diff) | |
| download | coreboot-8971ccd576a7b0edbd02101b0c3bc3541cb6a741.tar.xz | |
soc/intel: Move pch_misc_init() to common code
List of changes:
1. Move pch_misc_init() into common block code.
2. Remove redundant LPC functions from SoC directory and
refer from block/lpc directory.
3. Create macros for IO port 0x61 and 0x70 as applicable.
TEST=Able to build and boot hatch and tglrvp platform without seeing
any functional impact.
Change-Id: Ie36ee63869c076d251ccfa5409001d18f22600d7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/jasperlake')
| -rw-r--r-- | src/soc/intel/jasperlake/espi.c | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/src/soc/intel/jasperlake/espi.c b/src/soc/intel/jasperlake/espi.c index ef1ed953fb..0977857684 100644 --- a/src/soc/intel/jasperlake/espi.c +++ b/src/soc/intel/jasperlake/espi.c @@ -65,18 +65,6 @@ static void soc_mirror_dmi_pcr_io_dec(void) soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); } -static void pch_misc_init(void) -{ - uint8_t reg8; - - /* Setup NMI on errors, disable SERR */ - reg8 = (inb(0x61)) & 0xf0; - outb((reg8 | (1 << 2)), 0x61); - - /* Disable NMI sources */ - outb((1 << 7), 0x70); -}; - void lpc_soc_init(struct device *dev) { /* Legacy initialization */ |