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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2017-04-01 20:33:58 -0700 |
|---|---|---|
| committer | Lee Leahy <leroy.p.leahy@intel.com> | 2017-05-08 19:13:35 +0200 |
| commit | 16bc9bab2ab3b248f44bdf721ec83cdc21bcc32e (patch) | |
| tree | 4d52e7ae44b49d4f63b21c74a255c47389e6bfeb /src/soc/intel/quark/Makefile.inc | |
| parent | 52f29743b153e89ca38db5d7a207c676c4c70207 (diff) | |
| download | coreboot-16bc9bab2ab3b248f44bdf721ec83cdc21bcc32e.tar.xz | |
soc/intel/quark: Add SD/MMC test support
The SD/MMC test support consists of:
* Add Kconfig value to enable the SD/MMC test support.
* Add Kconfig value to enable the logging support.
* Add SD/MMC controller init code and read block 0 from each partition.
* Add logging code to snapshot the transactions with the SD/MMC device.
* Add eMMC driver for ramstage to call test code.
* Add romstage code to call test code.
* Add bootblock code to call test code.
TEST=Build and run on Galileo Gen2
Change-Id: I72785f0dcd466c05c1385cef166731219b583551
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/19211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/quark/Makefile.inc')
| -rw-r--r-- | src/soc/intel/quark/Makefile.inc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index 1d66e6beba..d0a7a932e8 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -33,6 +33,7 @@ verstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c romstage-y += i2c.c romstage-y += memmap.c romstage-y += reg_access.c +romstage-$(CONFIG_STORAGE_TEST) += storage_test.c romstage-y += tsc_freq.c romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c @@ -56,6 +57,8 @@ ramstage-y += memmap.c ramstage-y += northcluster.c ramstage-y += reg_access.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c +ramstage-y += sd.c +ramstage-$(CONFIG_STORAGE_TEST) += storage_test.c ramstage-y += tsc_freq.c ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c |