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| author | Eugene Myers <edmyers@tycho.nsa.gov> | 2020-01-21 16:46:16 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-04 18:54:01 +0000 |
| commit | ebc8423cbcb0bcd95c45e68cdf04af9f10be1bfe (patch) | |
| tree | 1bdfad8f25beaed979639b5e2f0b302d84f99045 /src/soc/intel/quark/acpi.c | |
| parent | c9ac0bcb9827ab2bef5fd7548eb13302cfd9c57d (diff) | |
| download | coreboot-ebc8423cbcb0bcd95c45e68cdf04af9f10be1bfe.tar.xz | |
soc/intel: Add get_pmbase
Originally a part of security/intel/stm.
Add get_pmbase to the intel platform setup code.
get_pmbase is used by the coreboot STM setup functions to ensure
that the pmbase is accessable by the SMI handler during runtime.
The pmbase has to be accounted for in the BIOS resource list so
that the SMI handler is allowed this access.
Change-Id: If6f6295c5eba9eb20e57ab56e7f965c8879e93d2
Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37990
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/quark/acpi.c')
| -rw-r--r-- | src/soc/intel/quark/acpi.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/quark/acpi.c b/src/soc/intel/quark/acpi.c index ffcd91f13d..5006b19d47 100644 --- a/src/soc/intel/quark/acpi.c +++ b/src/soc/intel/quark/acpi.c @@ -104,3 +104,10 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt) printk(BIOS_SPEW, " 0x%08x: RESET\n", fadt->reset_reg.addrl); } + +uint16_t get_pmbase(void) +{ + struct device *dev = pcidev_on_root(PCI_DEVICE_NUMBER_QNC_LPC, + PCI_FUNCTION_NUMBER_QNC_LPC); + return (uint16_t) pci_read_config32(dev, R_QNC_LPC_PM1BLK) & B_QNC_LPC_PM1BLK_MASK; +} |