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authorLee Leahy <leroy.p.leahy@intel.com>2016-07-20 08:58:58 -0700
committerLee Leahy <leroy.p.leahy@intel.com>2016-08-03 17:47:53 +0200
commit01728bb2ed1847dadf1429fafe0be2cb7876eed8 (patch)
treedac9a0682b205409038d4b742350ba28e2dc1af3 /src/soc/intel/quark/chip.c
parent3d0e3cf4b125dfda236d6978adea5f5d40fd78e8 (diff)
downloadcoreboot-01728bb2ed1847dadf1429fafe0be2cb7876eed8.tar.xz
soc/intel/quark: Prepare for FSP2.0 support
Split the original contents of romstage.c into car.c, romstage.c and fsp1_1.c. TEST=Build and run on Galileo Gen2 Change-Id: I6392d7382e383ea2087afa6bf45b1f087ba78d79 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15862 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/quark/chip.c')
-rw-r--r--src/soc/intel/quark/chip.c14
1 files changed, 1 insertions, 13 deletions
diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c
index 2fe2b75a4f..29b615213a 100644
--- a/src/soc/intel/quark/chip.c
+++ b/src/soc/intel/quark/chip.c
@@ -117,10 +117,7 @@ static void chip_init(void *chip_info)
| TS_LOCK_AUX_TRIP_PT_REGS_ENABLE));
/* Perform silicon specific init. */
- if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM))
- intel_silicon_init();
- else
- fsp_run_silicon_init(find_fsp(CONFIG_FSP_ESRAM_LOC), 0);
+ fsp_silicon_init();
}
static void pci_domain_set_resources(device_t dev)
@@ -150,12 +147,3 @@ struct chip_operations soc_intel_quark_ops = {
.init = &chip_init,
.enable_dev = chip_enable_dev,
};
-
-void soc_silicon_init_params(SILICON_INIT_UPD *upd)
-{
-}
-
-void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,
- SILICON_INIT_UPD *new)
-{
-}