soc/intel/quark: Set the UPD values for MemoryInit

Set the UPD values for MemoryInit.
*  Update the FspUpdVpd.h file which specifies the parameters for
   MemoryInit.
*  Add the necessary values to chip.h to enable values to come from
   the mainboard's devicetree.cb file
*  Add the parameters to the mainboard's devicetree.cb file
*  Locate the platform configuration database file (pdat.bin)
*  Copy the data values from the chip_info structure into the UPDs
*  Display the UPD values

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file:
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
   CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
   UEFIPAYLOAD.fd
*  Edit .config file and add the following lines:
   *  CONFIG_DISPLAY_UPD_DATA=y
*  Testing successful when the UPD data is displayed before the call to
   MemoryInit

Change-Id: Ic64f3d97eb43ea42d9b149769fc96bf78bf804f5
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13896
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)

1 files changed, 11 insertions, 1 deletions

diff --git a/src/soc/intel/quark/chip.h b/src/soc/intel/quark/chip.h
index 59c8793dfe..fc9890fde5 100644
--- a/src/soc/intel/quark/chip.h
+++ b/src/soc/intel/quark/chip.h
@@ -19,11 +19,21 @@
 #define _SOC_CHIP_H_
 
 #include <stdint.h>
+#include <fsp/util.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 
 struct soc_intel_quark_config {
-	uint32_t junk;
+	/*
+	 * MemoryInit:
+	 *
+	 * The following fields come from FspUpdVpd.h and are defined as PCDs
+         * for the FSP binary.  Data for these fields comes from the board's
+	 * devicetree.cb file which gets processed into static.c and then
+	 * built into the coreboot image.  The fields below contain retain
+	 * the FSP PCD field name.
+	 */
+	UINT16 PcdSmmTsegSize;
 };
 
 extern struct chip_operations soc_ops;