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authorLee Leahy <leroy.p.leahy@intel.com>2016-07-21 09:17:10 -0700
committerLee Leahy <leroy.p.leahy@intel.com>2016-08-03 17:31:39 +0200
commit14d09264a2b64c38bf4e5cf309947a8a2fbafc6d (patch)
tree5a259955ae9932c4dbc0c96864e7cb05410e8bf0 /src/soc/intel/quark/chip.h
parent1cfb555e713f57b86d6ae779704e2861e654b25c (diff)
downloadcoreboot-14d09264a2b64c38bf4e5cf309947a8a2fbafc6d.tar.xz
soc/intel/quark: Remove use of EDK-II macros and data types
Include assert.h to use coreboot's ASSERT macro. Replace the use of UINT32 data type with uint32_t. Replace the use of UINT8 data type with uint8_t. TEST=Build and run on Galileo Gen2 Change-Id: I0bb7e43ea570f7b20355c5d05675ebf593942e83 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15858 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/quark/chip.h')
-rw-r--r--src/soc/intel/quark/chip.h52
1 files changed, 26 insertions, 26 deletions
diff --git a/src/soc/intel/quark/chip.h b/src/soc/intel/quark/chip.h
index 66105eaa0b..b2396313f2 100644
--- a/src/soc/intel/quark/chip.h
+++ b/src/soc/intel/quark/chip.h
@@ -47,70 +47,70 @@ struct soc_intel_quark_config {
* the FSP PCD field name.
*/
- UINT32 FspReservedMemoryLength; /* FSP reserved memory in bytes */
+ uint32_t FspReservedMemoryLength; /* FSP reserved memory in bytes */
- UINT32 Flags; /* Bitmap of MRC_FLAG_XXX defs above */
- UINT32 tRAS; /* ACT to PRE command period in picoseconds */
+ uint32_t Flags; /* Bitmap of MRC_FLAG_XXX defs above */
+ uint32_t tRAS; /* ACT to PRE command period in picoseconds */
/* Delay from start of internal write transaction to internal read
* command in picoseconds
*/
- UINT32 tWTR;
+ uint32_t tWTR;
/* ACT to ACT command period (JESD79 specific to page size 1K/2K) in
* picoseconds
*/
- UINT32 tRRD;
+ uint32_t tRRD;
/* Four activate window (JESD79 specific to page size 1K/2K) in
* picoseconds
*/
- UINT32 tFAW;
- UINT8 DramWidth; /* 0=x8, 1=x16, others=RESERVED */
+ uint32_t tFAW;
+ uint8_t DramWidth; /* 0=x8, 1=x16, others=RESERVED */
/* 0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU
* support 1066 memory
*/
- UINT8 DramSpeed;
- UINT8 DramType; /* 0=DDR3,1=DDR3L, others=RESERVED */
+ uint8_t DramSpeed;
+ uint8_t DramType; /* 0=DDR3,1=DDR3L, others=RESERVED */
/* bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED */
- UINT8 RankMask;
- UINT8 ChanMask; /* bit[0] CHAN0_EN, others=RESERVED */
- UINT8 ChanWidth; /* 1=x16, others=RESERVED */
+ uint8_t RankMask;
+ uint8_t ChanMask; /* bit[0] CHAN0_EN, others=RESERVED */
+ uint8_t ChanWidth; /* 1=x16, others=RESERVED */
/* 0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED */
- UINT8 AddrMode;
+ uint8_t AddrMode;
/* 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE */
- UINT8 SrInt;
- UINT8 SrTemp; /* 0=normal, 1=extended, others=RESERVED */
+ uint8_t SrInt;
+ uint8_t SrTemp; /* 0=normal, 1=extended, others=RESERVED */
/* 0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver
* impedance control.
*/
- UINT8 DramRonVal;
- UINT8 DramRttNomVal; /* 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED */
- UINT8 DramRttWrVal; /* 0=off others=RESERVED */
+ uint8_t DramRonVal;
+ uint8_t DramRttNomVal; /* 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED */
+ uint8_t DramRttWrVal; /* 0=off others=RESERVED */
/* 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED */
- UINT8 SocRdOdtVal;
- UINT8 SocWrRonVal; /* 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED */
- UINT8 SocWrSlewRate; /* 0=2.5V/ns, 1=4V/ns, others=RESERVED */
+ uint8_t SocRdOdtVal;
+ uint8_t SocWrRonVal; /* 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED */
+ uint8_t SocWrSlewRate; /* 0=2.5V/ns, 1=4V/ns, others=RESERVED */
/* 0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED */
- UINT8 DramDensity;
- UINT8 tCL; /* DRAM CAS Latency in clocks */
+ uint8_t DramDensity;
+ uint8_t tCL; /* DRAM CAS Latency in clocks */
/* ECC scrub interval in miliseconds 1..255 (0 works as feature
* disable)
*/
- UINT8 EccScrubInterval;
+ uint8_t EccScrubInterval;
/* Number of 32B blocks read for ECC scrub 2..16 */
- UINT8 EccScrubBlkSize;
+ uint8_t EccScrubBlkSize;
- UINT8 SmmTsegSize; /* SMM size in MiB */
+ uint8_t SmmTsegSize; /* SMM size in MiB */
};
extern struct chip_operations soc_ops;