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author | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-13 17:13:39 -0700 |
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committer | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-14 23:54:54 +0100 |
commit | 1e24bf3f719f82c16fd577e87900e1aa0fd6605b (patch) | |
tree | 0e449830c5fbe7605b55e8d8e4dc7287c2c2af8c /src/soc/intel/quark/fsp1_1.c | |
parent | 66b0d55d326540e400ad3fa5130666dbd03b9694 (diff) | |
download | coreboot-1e24bf3f719f82c16fd577e87900e1aa0fd6605b.tar.xz |
soc/intel/quark: Pass S3 wake status to fsp_silicon_init
Fix build error with FSP 1.1. Pass the S3 wake status to
fsp_silicon_init.
TEST=Build and run on Galileo Gen2
Change-Id: I78150f737321db5b1b4d63b411fa6432ac30d080
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18805
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/quark/fsp1_1.c')
-rw-r--r-- | src/soc/intel/quark/fsp1_1.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/quark/fsp1_1.c b/src/soc/intel/quark/fsp1_1.c index ee10e38e60..1178031f8d 100644 --- a/src/soc/intel/quark/fsp1_1.c +++ b/src/soc/intel/quark/fsp1_1.c @@ -17,12 +17,12 @@ #include <fsp/util.h> #include <soc/ramstage.h> -void fsp_silicon_init(void) +void fsp_silicon_init(bool s3wake) { if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM)) intel_silicon_init(); else - fsp_run_silicon_init(find_fsp(CONFIG_FSP_ESRAM_LOC), 0); + fsp_run_silicon_init(find_fsp(CONFIG_FSP_ESRAM_LOC), s3wake); } void soc_silicon_init_params(SILICON_INIT_UPD *upd) |