soc/intel/quark: Add USB PHY initialization

Add register access support using register scripts.
Initialize the USB PHY using register scripts.

TEST=Build and run on Galileo Gen2

Change-Id: I34a8e78eab3c7314ca34343eccc8aeef0622798a
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14496
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

3 files changed, 65 insertions, 8 deletions

diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h
index 4f577cef8e..a912c4c807 100644
--- a/src/soc/intel/quark/include/soc/pci_devs.h
+++ b/src/soc/intel/quark/include/soc/pci_devs.h
@@ -25,9 +25,11 @@
 /* DEVICE 0 (Memroy Controller Hub) */
 #define MC_BDF		PCI_DEV(PCI_BUS_NUMBER_QNC, MC_DEV, MC_FUN)
 
-/* IO Fabric 1 */
-#define HSUART_DEVID	0x0936
+/* Device IDs */
+#define HSUART_DEVID		0x0936
+#define EHCI_DEVID		0x0939
 
+/* IO Fabric 1 */
 #define SIO1_DEV 0x14
 # define HSUART1_DEV SIO1_DEV
 # define HSUART1_FUNC 5
diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h
new file mode 100644
index 0000000000..934c75d0e5
--- /dev/null
+++ b/src/soc/intel/quark/include/soc/reg_access.h
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _QUARK_REG_ACCESS_H_
+#define _QUARK_REG_ACCESS_H_
+
+#include <fsp/util.h>
+#include <reg_script.h>
+#include <soc/QuarkNcSocId.h>
+
+enum {
+	USB_PHY_REGS = 1,
+};
+
+enum {
+	SOC_TYPE = REG_SCRIPT_TYPE_SOC_BASE,
+	/* Add additional SOC access types here*/
+};
+
+#define SOC_ACCESS(cmd_, reg_, size_, mask_, value_, timeout_, reg_set_)   \
+	_REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, SOC_TYPE,        \
+			       size_, reg_, mask_, value_, timeout_, reg_set_)
+#define REG_USB_ACCESS(cmd_, reg_, mask_, value_, timeout_) \
+	SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \
+		USB_PHY_REGS)
+#define REG_USB_READ(reg_) \
+	REG_USB_ACCESS(READ, reg_, 0, 0, 0)
+#define REG_USB_WRITE(reg_, value_) \
+	REG_USB_ACCESS(WRITE, reg_, 0, value_, 0)
+#define REG_USB_AND(reg_, value_) \
+	REG_USB_RMW(reg_, value_, 0)
+#define REG_USB_RMW(reg_, mask_, value_) \
+	REG_USB_ACCESS(RMW, reg_, mask_, value_, 0)
+#define REG_USB_RXW(reg_, mask_, value_) \
+	REG_USB_ACCESS(RXW, reg_, mask_, value_, 0)
+#define REG_USB_OR(reg_, value_) \
+	REG_USB_RMW(reg_, 0xffffffff, value_)
+#define REG_USB_POLL(reg_, mask_, value_, timeout_) \
+	REG_USB_ACCESS(POLL, reg_, mask_, value_, timeout_)
+#define REG_USB_XOR(reg_, value_) \
+	REG_USB_RXW(reg_, 0xffffffff, value_)
+
+void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address);
+uint32_t mdr_read(void);
+void mdr_write(uint32_t value);
+void mea_write(uint32_t reg_address);
+
+#endif /* _QUARK_REG_ACCESS_H_ */
diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h
index c2c7e9c03a..c344adac0a 100644
--- a/src/soc/intel/quark/include/soc/romstage.h
+++ b/src/soc/intel/quark/include/soc/romstage.h
@@ -23,13 +23,8 @@
 #endif
 
 #include <fsp/romstage.h>
-#include <fsp/util.h>
-#include <soc/QuarkNcSocId.h>
+#include <soc/reg_access.h>
 
-void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address);
-uint32_t mdr_read(void);
-void mdr_write(uint32_t value);
-void mea_write(uint32_t reg_address);
 uint32_t port_reg_read(uint8_t port, uint32_t offset);
 void port_reg_write(uint8_t port, uint32_t offset, uint32_t value);
 void report_platform_info(void);